Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation

Zergainoh, Nacer-Eddine; Tambour, L.; Jerraya, Ahmed

doi:10.1109/tvlsi.2006.874360

Cited by 3 publications

(1 citation statement)

References 29 publications

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“…Reutilizar componentes para aplicaciones de altas prestaciones de procesado de señal es una tarea que permite mejorar la productividad en el diseño, pero como se indica en [ZTJ06], es común que la integración de estos componentes en un sistema de manera automática dé problemas y resulte errónea debido a los retardos requeridos en las restricciones de la implementación.…”

Section: Hml [Ll95]unclassified

Implementación de Algoritmos de Procesado de Señal sobre FPGA: Especificación, Reutilización y Exploración del Espacio de Diseño

Marcos¹

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This PhD. thesis addresses the design and implementation of signal processing applications using reconfigurable FPGA platforms. This kind of platform exhibits high logic capability, incorporates dedicated signal processing elements and provides a low cost solution, which makes it ideal for the development of signal processing applications, where intensive data processing is required in order to obtain high performance.However, the cost associated to the hardware development on these platforms is high. While the increase in logic capacity of FPGA devices allows the development of complete systems, high-performance constraints require the optimization of operators at very low level. In addition to time constraints imposed by these applications, Area constraints are also applied related to the particular device, which force to evaluate and verify a design among different implementation alternatives. The design and implementation cycle for these applications can be tedious and long, being therefore normal that new FPGA models with a greater capacity and higher speed appear before completing the system implementation. Thus, the original constraints which guided the design of the system become useless.Different methods can be used to improve the productivity when developing these applications, and consequently shorten their design cycle. This PhD. Thesis focuses on the reuse of hardware components previously designed and verified. Although conventional HDLs allow the reuse of components already defined, their specification can be improved in order to simplify the process of incorporating new design components. Thus, a first part of the PhD. Thesis will focus on the specification of designs based on predefined components. This specification improves and simplifies the process of adding components to a description, but it also seeks to improve the quality of the design specified with better configuration options and even offering to report on features of the description.Hardware reuse of a component for its integration into a system largely depends on the information it offers. In this sense the conventional HDLs only provide together with the component description, the input/output interface and a set of parameters for its configuration, while other information is usually provided by external documentation. In the second part of the Thesis we will propose a formal way of encapsulation which aims to incorporate with the component description information that can be useful for its integration into other designs. This information will include features of the own implementation, but it will also support component configuration, and even information on how to configure and connect the component to carry out a function.Finally, the fast Fourier transform (FFT) will be chosen as a well-known signal processing application. It will be used as case study to illustrate the possibilities of porposed v specification and encapsulation formalisms. The objective of the FFT design is not only to show practical examples of the proposed s...

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Section: Hml [Ll95]unclassified

Implementación de Algoritmos de Procesado de Señal sobre FPGA: Especificación, Reutilización y Exploración del Espacio de Diseño

Marcos¹

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Automatic Code Generation for MPSoC Platform Starting From Simulink/Matlab : New Approach to Bridge the Gap between Algorithm and Architecture Design

Atat¹,

Zergainoh²

2008

2008 3rd International Conference on Information and Communication Technologies: From Theory to Applications

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isbn: 978-1-4244-1751-3International audienceThis paper deals with the system level design flow and methodology for rapid prototyping of multiprocessor systems on chip (MPSoC) starting from Matlab/Simulink specification. The rise of the abstraction level when designing the hardware (HW) and software (SW) parts of MPSoC permits to master the growing complexity of these systems. However, it generates a huge gap between the concepts of system level specification and those used for implementation and synthesis of HW/SW MPSoC. In this paper, we propose a new approach to establish a bridge between the system level specification in Matlab/Simulink and the HW/SW architecture at the implementation level

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Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design

Atat

Zergainoh

2007

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)

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ISBN: 0-7695-2896-1International audienceThe rise of the abstraction level when designing the hardware (HW) and software (SW) parts of multiprocessor systems on chip (MPSoC) permits to master the growing complexity of these systems. However, it generates a huge gap between the concepts of system level specification and those used for implementation and synthesis of HW/SW MPSoC. This paper deals with the system level design for rapid prototyping of MPSoC starting from Matlab/Simulink specification. We propose a new approach to establish a bridge between the system level specification and the HW/SW architecture at the implementation level

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Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation

Cited by 3 publications

References 29 publications

Implementación de Algoritmos de Procesado de Señal sobre FPGA: Especificación, Reutilización y Exploración del Espacio de Diseño

Implementación de Algoritmos de Procesado de Señal sobre FPGA: Especificación, Reutilización y Exploración del Espacio de Diseño

Automatic Code Generation for MPSoC Platform Starting From Simulink/Matlab : New Approach to Bridge the Gap between Algorithm and Architecture Design

Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design

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