(Invited) Heterogeneously Integrated III-V on Silicon for Future Nanoelectronics

Abstract

With the scaling of Si CMOS technology, each transistor has become smaller and faster, leading to unprecedented increase in microprocessor performance, while the rising number of transistors increases the power consumption in ICs [1]. The computing power and density of ICs is primarily constrained by power consumption and high-speed operation. Low-power consumption would imply lower heat dissipation, prolonged battery life and reduced cooling requirements, which all add up to significant reductions in cost and energy savings. Going forward transistor scaling will require the introduction of new materials, including III-V and Ge, and novel device architectures to reduce energy consumption. New materials and device structure innovation and their heterogeneous integration on Si could be a key enabler for lowering power consumption and enhance performance of microprocessor. There is a tremendous progress in III-V semiconductor industry in applications ranging from low-power and high-speed computing to photonic devices. Heterogeneous integration of high mobility III-V materials with Si substrate is one of the most promising ways to harvest the potential of III-Vs and prohibit the need for developing large area and expensive III-V wafers. Large lattice mismatch (4-19%) and thermal expansion differences between InAs (InSb) and Si leads to defects and dislocations, which adversely affect the channel mobility and degrades device performance. Although, there has been considerable progress in reducing dislocations using graded buffer, strained superlattices, thermal cycle annealing, and patterned growth; all of them failed to achieve low defect density and eliminate parallel conduction to the channel. Several challenges namely, low growth temperature, elimination of carrier freeze-out at 75K, and scalable buffer elude the successful integration of high-quality III-Vs on Si. To address these challenges, novel material innovations and radical changes in buffer architecture and device design are essential. The InGaAs quantum-well FET structures were heterogeneously integrated on Si substrate to address the low band gap III-V device structures on Si growth issues, and as a potential NMOS channel material for low-power logic. In order to achieve the APD-free III-V buffers on nonpolar Si substrate to address the defects and dislocations due to lattice mismatch and the high-quality InGaAs metamorphic QWFETs device structure growth on such buffer, careful design of various aspects of growth, buffer architecture and strain-relaxation is investigated using MBE. The relaxation state and the buffer layer grading scheme were evaluated using high-resolution x-ray rocking curve, as shown in Fig.

Energy band alignment of atomic layer deposited HfO2 oxide film on epitaxial (100)Ge, (110)Ge, and (111)Ge layers

“…Figure 2(b) shows the CL spectrum from 5 nm thick HfO 2 film and the band gap was determined to be 5.52 6 0.1 eV. The DE C can be calculated based on the measured DE v and the difference in bandgaps of HfO 2 and Ge, where DE g ¼ DE v þ DE c . Using Eq.…”

“…The DE V and DE C discontinuities at the HfO 2 /(110)Ge heterointerface were quantified using Eqs. (1) and (2) . Figures 3(a) and 3(b) show the Ge 3d CL spectrum and VBM of (110)Ge film as well as Hf 4f CL spectrum and VBM of 5 nm HfO 2 film, 4.…”

“…1 One attractive approach is to replace the Si channel with high intrinsic hole mobility Ge for p-channel and low effective carrier mass III-V material for n-channel material. [2][3][4][5] Alternative approach is different surface orientations to improve carrier mobility [6][7][8][9] and optimal channel direction for device speed. [10][11][12][13][14] Recently, semiconductor industry was replaced SiO 2 gate oxide by hafnium-based gate dielectric on Si complementary metal oxide semiconductor (CMOS) technology and demonstrated superior microprocessor performance compared to SiO 2 gate oxide.…”

Structural and band alignment properties of Al2O3 on epitaxial Ge grown on (100), (110), and (111)A GaAs substrates by molecular beam epitaxy

“…1 Recently, III-V compound semiconductors, namely, InGaAs, InAs, InSb, and InAsSb, [2][3][4][5][6][7][8] coupled with high-j gate dielectrics have been investigated for n-channel field-effect transistors. However, the demonstration of equivalent high-performance p-channel transistor is mandatory to realize energy-efficient CMOS logic.…”

Energy band alignment of atomic layer deposited HfO2 on epitaxial (110)Ge grown by molecular beam epitaxy

“…According to the International Technology Roadmap for Semiconductors, 1 channel materials with superior transport properties, high-j gate dielectric, and multi-gate transistor configuration in a CMOS logic device under 10 nm regime are required to achieve further increase in transistor drive current and resultant ULSI performance improvement. In recent years, low bandgap high electron mobility III-V compounds coupled with high-j gate dielectrics [2][3][4] have been demonstrated in n-channel device configuration operating at 0.5 V; [5][6][7][8] however, the demonstration of a high hole mobility p-channel device configuration along with high-j dielectric is mandatory to realize energy-efficient CMOS logic. For this reason, the enhancement of carrier transport properties in the channel using high hole mobility channel materials, 9-11 different surface orientations to improve the carrier mobility, 12,13 and optimal channel direction [14][15][16] have been proposed for further enhancement of CMOS devices.…”