(Invited) A Brief Review of Doping Issues in III-V Semiconductors

Jones, K. S.; Lind, Aaron G.; Hatem, C.; Moffatt, S.; Ridgeway, Mark C.

doi:10.1149/05303.0097ecst

Cited by 25 publications

(18 citation statements)

References 76 publications

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“…According to Kevin S. Jones group research, it demonstrated that elevating implantation temperature could help destroyed lattices with recovery to avoid amorphous layers [4,5,9]. Prior to annealing, 15nm protective layer Al 2 O 3 was deposited by ALD to prevent surface degradation, and the previous literature has proved that using Al 2 O 3 for capping layer could prevent surface degradation due to group V easily loss [6,7]. After capping Al 2 O 3 on In 0.53 Ga 0.47 As, they were annealed by MWA 1P(0.6kW)-4P(2.4kW) for 100 s and by RTA 450-750°C for 8 s, respectively.…”

Section: Experimental Schemementioning

confidence: 99%

Studies on Activation of High-Mobility III-V Group Semiconductor Materials by Using Microwave Annealing

Shih¹,

Lee²

2017

IJMSA

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Abstract:As semiconductors devices scale down, silicon transistors would reach its limitation below 10 nm. Researching for the novel materials, which could replace silicon, is important. In this study, the new potential materials III-V Group compound semiconductors which are ion implanted with low energy and low dose. In order to keep the ultra-shallow junction and get the best activation, the new annealing technology ─ microwave annealing (MWA) is employed. Microwave annealing is a processing with low energy and longer period. In contrast to the conventional high thermal annealing methods such as rapid thermal annealing (RTA), it is a process with high temperature and ultra-short time. However, the high temperature could cause the dopants diffusion and the ultra-short time might make the destroyed lattices repaired not completely. Ion implant with silicon at different temperature (80°C, and 150°C) into In 0.47 Ga 0.53 As(300 nm)/InP substrate, and annealed by low-energy MWA and traditional RTA, respectively to research SPER and electrical activation. By using Raman spectrum, we discover that using MWA energy 2.5P(1.5kW) for 100 s could make the III-V materials achieve SPER by repairing fully. From TEM images, the amorphous layer caused by ion implantation could be recovered to crystal lattices during implantation temperature at 150°C. After annealing by MWA 2.5P(1.5kW) for 100 s, the defects of stacking faults are repaired completely to attain SPER, and it can correspond the Raman results. By using SIMS analysis, it can demonstrate that MWA has better ability to control dopants diffusion. Finally, by using Photoluminescence spectroscopy analysis, the MWA energy 3P(1.8kW) for 100 s could just make silicon dopants get activation. After annealing by MWA 3.5P(2.1kW) for 100 s of implantation at 150°C has the best activation that it has the highest peak.

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Section: Experimental Schemementioning

confidence: 99%

Studies on Activation of High-Mobility III-V Group Semiconductor Materials by Using Microwave Annealing

Shih¹,

Lee²

2017

IJMSA

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“…Sub-15 nm ALD films of Al 2 O 3 have been shown to provide adequate surface protection at high annealing temperatures and have good etchant selectivity. [28][29][30] The complications associated with implantation and annealing of group III-As are not intractable, but the extra steps and difficulties associated with annealing may make growth doping more attractive in these materials.…”

Section: Ecs Journal Of Solid State Science and Technology 5 (5) Q12mentioning

confidence: 99%

Review—Dopant Selection Considerations and Equilibrium Thermal Processing Limits for n⁺-In_0.53Ga_0.47As

Lind

Aldridge

Hatem

et al. 2016

ECS J. Solid State Sci. Technol.

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An overview of various processing and dopant considerations for the creation of heavily-doped n-InGaAs is presented. A large body of experimental evidence and theoretical prediction point to dopant vacancy-complexing as the limiting mechanism for electrical activation in heavily Si doped InGaAs and GaAs. Dopant incorporation techniques which require thermal treatment steps to move dopants onto lattice sites like ion implantation and monolayer doping exhibit stable activation up to a limit of ≈1.5 × 1019 cm−3. Growth-based dopant incorporation methods have shown much higher (5 × 1019 cm−3) active concentrations but these activate concentrations are shown in multiple studies to be metastable. Other device specific process-flow constraints with respect to modern CMOS devices which may make some means of dopant incorporation method, or species selection more appropriate for a given application are also discussed.

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“…Indeed, silicon implantation has historically been used for III-V MOSFET implementation, but this technique suffers from two main disadvantages: (1) the surface and the crystal are damaged during the implantation, and (2) the doping level is limited to 1 × 10 19 atoms/cm 3 due to the amphoteric behavior of silicon [11]. For these reasons, two other unconventional solutions have been explored to further improve source/drain characteristics: (1) sulfur monolayer doping, which was successfully combined with Mo contacts to overcome the crystal damage induced by the implantation [12].…”

Section: Introductionmentioning

confidence: 99%

The Role of III-V Substrate Roughness and Deoxidation Induced by Digital Etch in Achieving Low Resistance Metal Contacts

2017

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To achieve low contact resistance between metal and III-V material, transmission-line-model (TLM) structures of molybdenum (Mo) were fabricated on indium phosphide (InP) substrate on the top of an indium gallium arsenide (InGaAs) layer grown by molecular beam epitaxy. The contact layer was prepared using a digital etch procedure before metal deposition. The contact resistivity was found to decrease significantly with the cleaning process. High Resolution Transmission & Scanning Electron Microscopy (HRTEM & HRSTEM) investigations revealed that the surface roughness of treated samples was increased. Further analysis of the metal-semiconductor interface using Energy Electron Loss Spectroscopy (EELS) showed that the amount of oxides (In x O y , Ga x O y or As x O y ) was significantly decreased for the etched samples. These results suggest that the low contact resistance obtained after digital etching is attributed to the combined effects of the induced surface roughness and oxides removal during the digital etch process.

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(Invited) A Brief Review of Doping Issues in III-V Semiconductors

Cited by 25 publications

References 76 publications

Studies on Activation of High-Mobility III-V Group Semiconductor Materials by Using Microwave Annealing

Studies on Activation of High-Mobility III-V Group Semiconductor Materials by Using Microwave Annealing

Review—Dopant Selection Considerations and Equilibrium Thermal Processing Limits for n⁺-In_0.53Ga_0.47As

The Role of III-V Substrate Roughness and Deoxidation Induced by Digital Etch in Achieving Low Resistance Metal Contacts

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(Invited) A Brief Review of Doping Issues in III-V Semiconductors

Cited by 25 publications

References 76 publications

Studies on Activation of High-Mobility III-V Group Semiconductor Materials by Using Microwave Annealing

Studies on Activation of High-Mobility III-V Group Semiconductor Materials by Using Microwave Annealing

Review—Dopant Selection Considerations and Equilibrium Thermal Processing Limits for n+-In0.53Ga0.47As

The Role of III-V Substrate Roughness and Deoxidation Induced by Digital Etch in Achieving Low Resistance Metal Contacts

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Review—Dopant Selection Considerations and Equilibrium Thermal Processing Limits for n⁺-In_0.53Ga_0.47As