Investigations of stress sensitivity of 0.12 CMOS technology using process modeling

Senez, V.; Hoffmann, T.; Robilliart, E.; Bouche, G.; Jaouen, H.; Lunenborg, M.M.; Carnevale, G.

doi:10.1109/iedm.2001.979642

Cited by 8 publications

(4 citation statements)

References 1 publication

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“…A mechanical analysis of the entire process flow (i.e. : Front (FEOL) and Back (BEOL) End of Line) of a 0.12 CMOS technology has been also performed [46]. This technology uses minimum active areas of the order of 0.08µm 2 and minimum edge size of 0.16µm isolated by Shallow Trenches (STI).…”

Section: Validation and Applicationsmentioning

confidence: 99%

Numerical analysis of the process-induced stresses in silicon microstructures

Senez

Hoffmann²,

Armigliato

et al. 2004

SPIE Proceedings

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Residual stresses can significantly affect the performances of silicon micro-structures. The understanding of the residual stress growth during their processing is of great importance. However, the experimental tracing of the stresses at the various stages of the machining is still almost impossible. Quantitative modelling of these problems is the alternative to provide guidelines for the minimization of the residual stresses. In this paper, we describe a technology computer aided design homemade tool, IMPACT. The mechanical models and the numerical implementation are presented. We give details about our methodology to calibrate and validate our implementation. The originality of this study lies in i) the capability to simulate almost all the sources of stress taking into account of the complex rheological behaviours of the materials, ii) the experimental determination of the mechanical properties of various thin film materials and iii) the validation of the calculations by direct comparisons with measured deformations in the micro-structures.

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Section: Validation and Applicationsmentioning

confidence: 99%

Numerical analysis of the process-induced stresses in silicon microstructures

Senez

Hoffmann²,

Armigliato

et al. 2004

SPIE Proceedings

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“…With the continuous downscaling of CMOS technology, shallow trench isolation (STI) induced mechanical stress increases with the shrinkage of the device active area. Many processing steps individually or collectively contribute to the development of STI stress, such as liner oxidation, highdensity-plasma (HDP) oxide deposition, thermal oxidation processes after STI formation, etc [1]. STI stress results in a strained region in the active area, thus changing the silicon bandgap [2], the diffusivity of impurities in silicon [3], the mobility of both electrons and holes [4] and so on.…”

Section: Introductionmentioning

confidence: 99%

A comprehensive study of reducing the STI mechanical stress effect on channel-width-dependent I_dsat

Xin

et al. 2007

Semicond. Sci. Technol.

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In this paper, the complex behavior of saturation drain current (I dsat ) dependence on channel width was investigated. We compared two types of devices and concluded that the variation of I dsat with changing width is determined by both the y-direction shallow trench isolation mechanical stress (y-stress) effect and the delta width effect. Moreover, a semi-empirical formula was proposed to describe the I dsat dependence on channel width, taking into account these two effects. To reduce the STI stress, we examined several process steps that may contribute to the stress development, and found that a high temperature post-liner-anneal step can obviously reduce the stress effect.

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“…On the other hand, several studies have reported on width dependence of hot carrier reliability for MOS transistor with LOCOS isolation and attributed the worsening HC reliability to mechanical constraint arising from the proximity of the bird's beak structure [157], [158]. When the transistor is further scaled, there have been numerous reports showing that the fresh device characteristics and oxide breakdown can also be degraded by the presence of large mechanical stress [159]- [169]. The mechanical stress is originated from shallow trench isolation (STI) [159]- [165] and thin films [165]- [169].…”

Section: Width Dependence Of Nbtimentioning

confidence: 99%

“…When the transistor is further scaled, there have been numerous reports showing that the fresh device characteristics and oxide breakdown can also be degraded by the presence of large mechanical stress [159]- [169]. The mechanical stress is originated from shallow trench isolation (STI) [159]- [165] and thin films [165]- [169].…”

Section: Width Dependence Of Nbtimentioning

confidence: 99%

Experimental and theoretical studies of negative bias temperature instability in ultra-thin gate dielectrics

Tan¹

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This thesis is a collection of my research work at the Nanyang Technological University, as well as the dedicated guidance, encouragement, and support from A/Prof. Chen Tu Pei, who has served as my research advisor during the entire course of research. Without his investment of time and energy this research would never reach the fruition. I also deeply appreciate Dr. Lap Chan from Chartered Semiconductor Manufacturing for his guidance, suggestions and support throughout my research at NTU and Chartered. I am further indebted to Dr. Ang Chew Hoe for his continuous technical support during all these years. I would like to thank Soon Jiamei, who generously shared her expertise and knowledge in first-principles modeling with me. The award of a research scholarship by the NTU and A-Star is also gratefully acknowledged. Some of my fondest memories at Chartered are of my fellowship with those graduate students in the Special Project group. They have brought insight, intelligence, entertainment, and friendship, which have made my life at, Chartered an unforgettable one. Finally, I would like to express my deeply gratitude to my family especially my parent (Tan Yu long and Yau Chau Hwai) for their love, care, understanding, support and encouragement during all these years. Lastly, I thank my wife, Wendy Lee, without her patience, continuous support and strong belief, all these things would have never been possible.

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Investigations of stress sensitivity of 0.12 CMOS technology using process modeling

Cited by 8 publications

References 1 publication

Numerical analysis of the process-induced stresses in silicon microstructures

Numerical analysis of the process-induced stresses in silicon microstructures

A comprehensive study of reducing the STI mechanical stress effect on channel-width-dependent I_dsat

Experimental and theoretical studies of negative bias temperature instability in ultra-thin gate dielectrics

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Investigations of stress sensitivity of 0.12 CMOS technology using process modeling

Cited by 8 publications

References 1 publication

Numerical analysis of the process-induced stresses in silicon microstructures

Numerical analysis of the process-induced stresses in silicon microstructures

A comprehensive study of reducing the STI mechanical stress effect on channel-width-dependent Idsat

Experimental and theoretical studies of negative bias temperature instability in ultra-thin gate dielectrics

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A comprehensive study of reducing the STI mechanical stress effect on channel-width-dependent I_dsat