Investigation on the Initial Hot-Carrier Injection in P-LDMOS Transistors With Shallow Trench Isolation Structure

Su, R.Y.; Chiang, Po-Jui; Gong, Jeng; Huang, Tsung Yi; Tsai, Chien‐Hsiung; Chou, Charles C.-K.; Liu, C.M.

doi:10.1109/ted.2008.2006922

Cited by 9 publications

(3 citation statements)

References 13 publications

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“…Figure 6 shows the two-dimension distribution of the ii rate when the device was stressed at V gs = 4 V and V ds = 500 V. Figure 6 illustrates that the maximum ii rate is located at the Si/SiO 2 interface because the current flows along the surface mostly for the device. However, for most HV MOSFETs, the current flows in the body for the surface electric field and result in the ii rate maximal occurs in the body [10,11]. Based on the previous analysis, the degradation of R on is dominated by the maximum ii rate along the Si/SiO 2 interface.…”

Section: High V Ds and Low V Gs Stressing Conditionmentioning

confidence: 91%

Investigations of hot-carrier-induced degradation for 700 V n-LDMOS transistor under different stress conditions

Zhang¹,

Liu²,

Sun³

et al. 2013

IETE J Res

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The hot-carrier reliability of a 700 V n-LDMOS transistor under different stress conditions is investigated in detail. For the high drain voltage (V ds ) condition, the degradation of the saturate drain current (I dsat ) is different from the on-resistance (R on ) degradation for the change of the dominated degradation mechanism. Moreover, the serious R on degradation has identical variation tendency with substrate current (I sub ) because the maximum impact ionization occurs at the surface of the drift region. However, for the high gate voltage (V gs ) condition, the most important degradation is the threshold voltage (V th ). We found that the V th degradation has an exponential relationship with V gs . In addition, it is also observed that the thick field oxide results in strong and rapid recovery of the R on degradation.

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Section: High V Ds and Low V Gs Stressing Conditionmentioning

confidence: 91%

Investigations of hot-carrier-induced degradation for 700 V n-LDMOS transistor under different stress conditions

Zhang¹,

Liu²,

Sun³

et al. 2013

IETE J Res

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show abstract

“…Recently, the two‐stage hot‐carrier‐induced device degradation, i.e. the device degrades faster at the beginning of stress but the degradation tends to saturate as the stress time is longer, has been reported in n‐type and p‐type LDMOS transistors [3–5]. However, the mechanisms responsible for the reported two‐stage device degradation are not consistent.…”

Section: Introductionmentioning

confidence: 99%

“…However, the mechanisms responsible for the reported two-stage device degradation are not consistent. One possible reason is that the design of the LDMOS transistors used in [3][4][5] differs significantly as the devices are designed to meet different high-voltage applications. In this Letter, we investigate hot-carrier-induced device degradation in high-voltage p-type LDMOS transistors, and the two-stage degradation phenomenon is also observed.…”

mentioning

confidence: 99%

Two‐stage hot‐carrier‐induced degradation of p‐type LDMOS transistors

Chen

2014

Electron. lett.

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Hot-carrier-induced device degradation of high-voltage p-type lateral diffused metal-oxide semiconductor (LDMOS) transistors is investigated. A two-stage linear region drain current (I Dlin) shift (I Dlin shift increases rapidly at the beginning of stress but tends to saturate when the stress time is longer) is observed. Technology computer-aideddesign simulations and direct current current-voltage measurement results suggest that the decrease of residual fabrication interface traps (N IT) leads to an initial increase in I Dlin shift. On the other hand, two competing mechanisms, i.e. increase in N IT generation and increase in electron trapping, are responsible for the saturated I Dlin shift when the stress time is longer.

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Compact Modelling of the Hot-Carrier Degradation of Integrated HV MOSFETs

Alagi

2014

Hot Carrier Degradation in Semiconductor Devices

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Investigation on the Initial Hot-Carrier Injection in P-LDMOS Transistors With Shallow Trench Isolation Structure

Cited by 9 publications

References 13 publications

Investigations of hot-carrier-induced degradation for 700 V n-LDMOS transistor under different stress conditions

Investigations of hot-carrier-induced degradation for 700 V n-LDMOS transistor under different stress conditions

Two‐stage hot‐carrier‐induced degradation of p‐type LDMOS transistors

Compact Modelling of the Hot-Carrier Degradation of Integrated HV MOSFETs

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