Investigation of Short Channel Effects (SCEs) and Analog/RF Figure of Merits (FOMs) of Dual-Material Bottom-Spacer Ground-Plane (DMBSGP) FinFET

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The main aim of this work is to study the effect of symmetric and asymmetric spacer length variations towards source and drain on n-channel SOI JL vertically stacked (VS) nanowire (NW) FET at 10 nm gate length (L G ). Spacer length is proved to be one of the stringent metrics in deciding device performance along with width, height and aspect ratio (AR). The physical variants in this work are symmetric spacer length (L SD ), source side spacer length (L S ) and drain side spacer length (L D ). The simulation results give highest I ON /I OFF ratio with L D variation compared to L S and L SD , whereas latter two variations have similar effect on I ON /I OFF ratio. At 25 nm (2.5 × L G ) of L D , the device gives appreciable ON current with the highest I ON /I OFF ratio (2.19 × 10 8 ) with optimum subthreshold slope (SS) and ensures low power and high switching drivability. Moreover, it is noticed that among optimal values of L S and L D , the device I ON /I OFF ratio has an improvement of 22.69% as compared to other variations. Moreover, the effect of various spacer dielectrics on optimized device is also investigated. Finally, the CMOS inverter circuit analysis is performed on the optimized symmetric and asymmetric spacer lengths.

Section: Spacer Dielctric Optimizationmentioning

confidence: 99%

Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching

Sreenivasulu

Narendar

2022

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“…The potential distribution is more towards the drain and is minimal towards the channel and source side which reduces SCEs. [19,20]. 3.…”

Section: Device Structure and Simulation Setupmentioning

confidence: 99%

Design and Temperature Assessment of Junctionless Nanosheet FET for Nanoscale Applications

Sreenivasulu

Narendar

2021

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Nano-sheets are the revolutionary change to overcome the limitations of FinFET. In this paper, the temperature dependence of 10 nm junctionless (JL) nano-sheet FET performance on DC, analog and RF characteristics are investigated for the first time using extended source/drain and with high-k gate stack. The detailed DC performance analysis like transfer characteristics (ID-VGS), output characteristics (ID-VDS), DIBL, SS and ION/IOFF ratio are evaluated from 200 K to 350 K. We also analyzed the temperature effect on the ON-OFF performance metric (Q), dynamic power, and power consumption. Furthermore, to understand the device performance on various process parameters like doping, and work function variations are presented at 300 K. The proposed device exhibits good ION/IOFF switching behaviour with IOFF reaching less than nA for all temperatures. The cut-off frequency (ft) is determined to be in the THz range and the ON-OFF performance metric (Q) ranges between 1.5 to 2.2 μS-dec/mV at LG of 10 nm. Furthermore, the scaling effect of nano-sheet at various gate lengths (LG = 5 nm, 8 nm, 10 nm, 14 nm, and 20 nm) are also presented. From simulation analysis we notice that analog/RF performance parameters of a JL nano-sheet FET are less sensitive to temperature variations. At extremely scaled LG the nano-sheet FET exhibits lower power consumption and dynamic power and comparatively decreases with increase in temperature. The proposed nano-sheet FET demonstrates as a strong potential contender for low-power and high-frequency applications at nano-regime.

“…Cache memory which is made of SRAM cell [9][10][11] occupies 50% of area in processor the leakage power due to cache memory in processor is the major source of power dissipation [12]. Now a days SRAM is operating in nanometer range in electronic gadgets so, the power dissipation in SRAM should be as low as possible in which leakage currents has to be less and speed should be more.…”

Section: Static Random Access Memory (Sram)mentioning

confidence: 99%

“…FinFET reduces short channel effects by wrapping gate over channel from four sides. Due to continuous scaling FinFET faces several challenges in terms of cost effective, patterning, layout, device performance [9][10][11][12]. Due to several advantages FinFET can be used in variety of application such as terrestrial systems, infrared detectors, space, satellite communication, nuclear reactor, military [12][13].…”

Section: Introductionmentioning

confidence: 99%

Reliability and Power Analysis of FinFET Based SRAM

Navaneetha¹,

Bikshalu

2021

Demand for accommodating more and new functionalities within a single chip such as SOC needs a novel devices and architecture such as FinFET device instead of MOSFET. FinFET is emerged as nonplanar, multigate device to overcome short channel effects such as subthreshold swing deterioration, drain induced barrier lowering, threshold voltage roll off which degrade circuit performance. As the need of device technology is mounting in electronic gadgets the important parameters are taken into consideration such as low leakage, high reliability, low power dissipation, and high operating speed.Reliability is one of key considerations in converting a proof of concept into reality. In this work Reliability of FinFET device is studied experimentally according to ITRS (international technology roadmap for semiconductor) roadmap using several standard test protocols such as multiple current stressing, harsher environment conditions, and effect of electromigration. Furthermore, power analysis of FinFET based SRAM is done by using 7nm bsimcmg PTM les in mentor graphics tool. The FinFET based SRAM shown low leakage, power dissipation, delay compared to existing conventional MOSFET based SRAM.