Investigation of Reliability Characteristics in NMOS and PMOS FinFETs

Liao, Wen‐Shiang; Liaw, Yie-Gie; Tang, Mao-Chyuan; Chakraborty, Sandeep; C, Liu

doi:10.1109/led.2008.2000723

Cited by 34 publications

(5 citation statements)

References 13 publications

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“…Apart from investigating their electrical performance, the reliability of highly scaled FinFETs becomes of major concern and has continuously received the attention of research community [3,4]. Generally, the FinFETs experience multiple temporal degradations (i.e.…”

Section: Introductionmentioning

confidence: 99%

Spice modeling of oxide and interface trapped charge effects in fully-depleted double-gate FinFETs

Janković

Pesic-Brdjanin

2015

J Comput Electron

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As is the case with conventional planar MOS transistors, the electrical characteristics of highly-scaled multi-gate field-effect transistors (FinFETs) also suffer from temporal degradations occurring due to hot-carrier injection, bias temperature instability and/or ionizing-radiation damage. The FinFETs aging is caused by cumulative contribution of the generation of oxide/Si interface traps and positively charged defects within the gate oxide. The accurate capturing of the dynamic contribution of the both trapped charges by the FinFET electrical models in Spice simulations is important for lifetime prediction and verification of long-term performance of advanced CMOS ICs. In this paper, the auxiliary sub-circuit is described aimed for including the effects of oxide and interface trapped charges in Spice electrical models of fully-depleted double-gate FinFETs. The efficiency of the proposed sub-circuit for modeling the aging effects in double-gate FinFETs is verified using two-dimensional TCAD device simulations.

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Section: Introductionmentioning

confidence: 99%

Spice modeling of oxide and interface trapped charge effects in fully-depleted double-gate FinFETs

Janković

Pesic-Brdjanin

2015

J Comput Electron

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“…Table 2 summarizes several reported strain schemes, including uniaxial, biaxial, and hybrid schemes [4,[7][8][10][11][12][13][26][27][28][29][30][31][32]. Some exciting strain schemes may achieve current enhancement near 80%.…”

Section: Benchmarksmentioning

confidence: 99%

Extension of Moore's Law via Strained Technologies- The Strategies and Challenges

Chung

2011

ECS Trans.

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For recent manufacturable CMOS technologies to extend the Moore's law, the interest in the strain engineering has been speed-up in recent years as a need in further scaling of CMOS devices for high speed and low power applications. Among those reported strain schemes [1-10], process-induced stress technique [1,6,10], strained-SiGe channel devices [3,8], substrate engineering, and hybrid substrate technology [9] have been attractive for high speed and low power logic CMOS technologies. As a consequence, strain-silicon technology has lasted for several generations beyond the 90nm generation node and it now comes to the cross-road of whether we want to use the planar CMOS structure at 20nm-16nm node. Strained technology seems to be one of the efficient approaches whatever the changes of device structure might be. Although some exciting strain schemes may achieve current enhancement that are expected, the reliability issues of strain CMOS devices need to be taken into consideration in the using of strained structures [11][12]. Also, with the further scaling of device dimensions, variability becomes increasingly important. More efforts on the study of strain-induced reliability, variability, device drain current enhancement etc., become more interested and raised more attention.In this talk, the strain-silicon technology since 90nm generation node will be first introduced. Then, the reliability and the design guideline for a trade-off between performance and reliability will be addressed. A technology roadmap in terms of the ballistic transport theory will be demonstrated. Then, the variability of the strained CMOS devices will be tackled, in which a more recently developed discrete dopant profiling [13] in the monitoring of the Ge and Carbon out-diffusion will be demonstrated. Finally, the strategies of strained-silicon device design with the trade-off between reliability, variability, and performance will be introduced. References

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“…For the FinFET structure, the general difficulties in device performance comprise the silicon fin (Si-fin) formation, gate stack, spacer isolation and Si-fin junction integrity [2][3][4]. These issues sometimes degrade the development speed.…”

Section: Introductionmentioning

confidence: 99%

Performance characteristics of p-channel FinFETs with varied Si-fin extension lengths for source and drain contacts

Liaw

Liao

Wang

et al. 2017

Физика И Техника Полупроводников

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The length of Source/Drain (S/D) extension (L SDE ) of nano-node p-channel FinFETs (pFinFETs) on SOI wafer influencing the device performance is exposed, especially in drive current and gate/S/D leakage. In observation, the longer L SDE pFinFET provides a larger series resistance and degrades the drive current (I DS ), but the isolation capability between the S/D contacts and the gate electrode is increased. The shorter L SDE plus the shorter channel length demonstrates a higher trans-conductance (Gm) contributing to a higher drive current. Moreover, the subthreshold swing (S.S.) at longer channel length and longer L SDE represents a higher value indicating the higher amount of the interface states which possibly deteriorate the channel mobility causing the lower drive current.

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Investigation of Reliability Characteristics in NMOS and PMOS FinFETs

Cited by 34 publications

References 13 publications

Spice modeling of oxide and interface trapped charge effects in fully-depleted double-gate FinFETs

Spice modeling of oxide and interface trapped charge effects in fully-depleted double-gate FinFETs

Extension of Moore's Law via Strained Technologies- The Strategies and Challenges

Performance characteristics of p-channel FinFETs with varied Si-fin extension lengths for source and drain contacts

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