Investigation of Re-Program Scheme in Charge Trap-Based 3D NAND Flash Memory

Abstract

Early retention or initial threshold voltage shift (IVS) is one of the key reliability challenges in charge trapping memory (CTM) based 3D NAND flash. Re-program scheme was introduced in quad-level-cell (QLC) NAND flash [1]-[4], and the IVS improvement by re-program scheme was reported. In this work, it is found that re-program can suppress ~81% of IVS in 3D NAND, which is much more significant than that of 2D NAND ~50% [5]. The mechanisms of IVS improvement by re-program scheme in 3D NAND are investigated.

A Review of Cell Operation Algorithm for 3D NAND Flash Memory

“…gram operation, improving both vertical and lateral charge loss [55]. As shown in Figure 7, the negative counter pulse scheme was also suggested [48].…”

“…Moreover, the electrons stored in the charge trap layer undergo lateral migration through silicon nitride connected over the entire WLs, intensifying retention loss [53,54]. To improve this, a reprogram method in which program operation is performed once again in a state where retention loss has occurred right after first program operation, improving both vertical and lateral charge loss [55]. As shown in Figure 7, the negative counter pulse scheme was also suggested [48].…”

Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory

“…The Vt distribution of the DMY0 at lower deck top position shifts higher than that of the DMY1 (at upper deck bottom position) after two erase pulses. Due to interference impact, the higher DMY0 Vt may impact the nearby WL Vt distribution such as WLn, which lead to WLn Vt disturbance [14][15][16][17].…”

“…Micromachines 2023,14, 1916. https://doi.org/10.3390/mi14101916 https://www.mdpi.com/journal/micromachines…”