Investigation of Program Saturation in Scaled Interpoly Dielectric Floating-Gate Memory Devices

Beug, M. F.; Chan, N.; Hoehr, T.; Mueller-Meskamp, Lars; Specht, Michael

doi:10.1109/ted.2009.2024020

Cited by 23 publications

(7 citation statements)

References 10 publications

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“…On account of the electric field direction in the gate-stack under programming conditions and under the reasonable assumption of a negligible role played by holes in the current flows through the gate-stack, this makes a weak electron leakage from the FG to the CG through the IGD (and not trapping therein) during the ISPP pulses the most likely source of the negative V T values observed in our analysis. Note, in this regard, that the existence of an electron leakage through the IGD during programming has already been reported in the past [25], referring, however, to cells with an extremely scaled IGD thickness and high programming voltages. Thanks to the possibility of detecting single-electron changes in the FG charge offered by our experimental test, Fig.…”

Section: B Electron Leakage From the Fgmentioning

confidence: 88%

“…When V PV is low, cells complete their program operation when n out is still much less than n in , meaning that the standard deviation of the V T coming from the last programming pulse is still dependent only on the electron injection process and equals σ V T (q V T /C pp ) 1/2 . When, instead, V PV is so high that n out becomes comparable to n in , leading to a reduction in V T with respect to V s [25], the net number of electrons stored in the FG during the last programming pulse results from the difference in the number of injected and emitted electrons. As a consequence, σ V T at the last programming pulse is higher than that given only by the statistical injection of electrons, as shown in Fig.…”

Section: Programming Accuracymentioning

confidence: 99%

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Investigation of the Program Operation of NAND Flash Cells With a Single-Electron Resolution

Nicosia

Compagnoni

Paolucci

et al. 2016

IEEE Trans. Electron Devices

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This paper exploits the possibility of monitoring the floating-gate (FG) charge of state-of-the-art NAND Flash arrays with a single-electron resolution to investigate in detail the program operation and some previously inaccessible technological parameters. In particular, the analysis leads to the assessment of the statistical distribution of the FG to controlgate capacitance and of the leakage current from the FG through the intergate dielectric during the programming pulses. Results highlight that resolving the FG charge at the single-electron level opens new prospects for the investigation of the operation and the parameters of NAND Flash arrays.

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Section: B Electron Leakage From the Fgmentioning

confidence: 88%

Section: Programming Accuracymentioning

confidence: 99%

Investigation of the Program Operation of NAND Flash Cells With a Single-Electron Resolution

Nicosia

Compagnoni

Paolucci

et al. 2016

IEEE Trans. Electron Devices

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“…It is evident that the calibration circuit composed of FG transistors with higher coupling ratios exhibits a faster convergence speed due to its superior capabilities of channel control. 31,32) Consequently, the final V sen voltage obtained at the sensing terminal is higher than in circuits employing transistors with lower coupling ratios. 12.…”

Section: Discussionmentioning

confidence: 99%

Advanced self-convergent calibration for selenized two-dimensional film gas sensors

Liu,

Shen,

Wang

et al. 2024

Jpn. J. Appl. Phys.

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This research presents an innovative gas sensor system featuring a selenized 2D-film as its primary sensing material, integrated with metal-gate-coupled floating gate devices to enable self-convergent calibration. The inherent variability in resistance levels of 2D gas-sensing materials across different devices has been a significant challenge, resulting in substantial output signal deviations within the sensing circuit. To address this issue, we introduce a novel self-convergent operational technique, which effectively mitigates the impact of resistance variations, thereby enhancing the precision and reliability of gas sensing outcomes. Our proposed gas sensor system promises to deliver consistent and accurate results, even in the presence of device-to-device resistance variations, making it a valuable contribution to the field of gas sensing technology. This work holds substantial potential for various applications requiring highly accurate gas detection and quantification.

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“…When switching to a fully planar cell architecture such as in [2] [3], where no wraparound is used at all, the coupling ratio (CR) is much lower than in traditional NAND cells. Therefore the electric field across the IGD is much higher and conventional ONO IGD solutions would be far to leaky during the programming operation, leading to programming saturation as the current through the IGD becomes similar to the current through the tunnel oxide [4].…”

Section: Introductionmentioning

confidence: 99%

Experimental study of programming saturation in low-coupling planar high-k/metal gate nand flash memory cells using a dedicated test structure

Blomme

Tan

Souriau

et al. 2014

2014 IEEE 6th International Memory Workshop (IMW)

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Fully planar NAND Flash arrays operate with very low coupling ratio (CR), and the CR reduces even further when scaling below 20 nm half-pitch. As a consequence, they suffer from programming saturation due to excessive leakage through the intergate dielectic (IGD) if no special precautions (such as the use of high-k IGD or hybrid floating gate) are taken. In this work, we investigate the dependence on the coupling ratio of programming saturation by using a dedicated test structure: by using a device with 8 wordlines sharing the same floating gate (FG), it is possible to program this device with any arbitrarily reduced effective coupling ratio, showing which programming window can be achieved.We demonstrate that the used devices with polySi\TiN FG and HfAlO\Al2O3\HfAlO IGD stack are suitable for operation with a coupling ratio down to 35% with 4V programming window above the fresh Vth. This coupling ratio corresponds to fully planar memory cells with 10 nm half-pitch, showing that programming saturation is not a showstopper for scaling down to 10nm node fully planar Flash memory cells.

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Investigation of Program Saturation in Scaled Interpoly Dielectric Floating-Gate Memory Devices

Cited by 23 publications

References 10 publications

Investigation of the Program Operation of NAND Flash Cells With a Single-Electron Resolution

Investigation of the Program Operation of NAND Flash Cells With a Single-Electron Resolution

Advanced self-convergent calibration for selenized two-dimensional film gas sensors

Experimental study of programming saturation in low-coupling planar high-k/metal gate nand flash memory cells using a dedicated test structure

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