Investigation of process induced stress in the channel of a SiGe embedded source/drain Ge-FinFET architecture

Sinha, Kunal; Chattopadhyay, Sanatan; Rahaman, Hafizur

doi:10.1109/isdcs.2018.8379632

Cited by 4 publications

(3 citation statements)

References 25 publications

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“…[1] The present mainstream fin field-effect transistor (FinFET) technology, which was introduced to overcome limitations of planer technology, is facing serious scaling challenges beyond the 5-nm node. [2][3][4] To improve electrostatic integrity, the adoption of nanowire (NW) or nanosheet (NS) GAA device structure is expected to be necessary for shorter gate length in the future node. [5][6][7] Although GAA device with compatible processes is a natural extension of FinFET, it still requires some disruptive technological breakthroughs before mass production, such as inner spacer, S/D epitaxial grown, multiple Vt. [8][9][10] Meanwhile, SiGe high mobility channel FinFET has also been proposed as a promising candidate to replace Si Fin-FET due to its higher hole mobility, better negative bias temperature instability (NBTI) reliability than Si.…”

Section: Introductionmentioning

confidence: 99%

Narrowed Si_0.7Ge_0.3 channel FinFET with subthreshold swing of 64 mV/Dec using cyclic self-limited oxidation and removal process

Liu

Wang

2023

Chinese Phys. B

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In this work, a narrowed Si0.7Ge0.3 channel FinFET device using a precise cyclic wet treatment process is demonstrated in detail. Si0.7Ge0.3 fin/per side of 0.63nm can be accurately removed in each cycle by utilizing a self-limited oxidation with 40% HNO3 solution for 40 s and oxidation removal with 1% HF solution for 10 s. As a result, after the dummy gate removal, the fin width of Si0.7Ge0.3 can be narrowed from 20nm to 8nm by utilizing 10 cycles of this wet treatment process. Compared with the conventional Si0.7Ge0.3 FinFET under the similar process, the narrowed Si0.7Ge0.3 channel FinFET using this newly developed wet treatment process can realize a stronger gate control capability because its subthreshold slope can be reduced by 24%, improved from 87 to 64 mV/dec.

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Section: Introductionmentioning

confidence: 99%

Narrowed Si_0.7Ge_0.3 channel FinFET with subthreshold swing of 64 mV/Dec using cyclic self-limited oxidation and removal process

Liu

Wang

2023

Chinese Phys. B

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“…It is shown that 20% Ge content in the in situ doped SiGe alloy exhibits approximately two orders of magnitude lower 2 of 9 ρ c than the ion implanted SiGe with the same Ge content. In [23] a simulation study of As doped Si 0.75 Ge 0.25 embedded stressors in a Ge FinFET fabricated on germanium-on-insulator (GOI) substrates is presented. The authors show a three-fold improvement in the device current at the ON state (I ON ), achieved with 25% Ge in the SiGe stressor.…”

Section: Introductionmentioning

confidence: 99%

Selective Epitaxial Growth of In Situ Doped SiGe on Bulk Ge for p+/n Junction Formation

et al. 2020

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Epitaxial in situ doped Si0.73Ge0.27 alloys were grown selectively on patterned bulk Ge and bulk Si wafers. Si0.73Ge0.27 layers with a surface roughness of less than 3 nm were demonstrated. Selectively grown p+Si0.73Ge0.27 layers exhibited a resistivity of 3.5 mΩcm at a dopant concentration of 2.5 × 1019 boron atoms/cm3. P+/n diodes were fabricated by selectively growing p+- Si0.73Ge0.27 on n-doped bulk Ge and n-doped Si wafers, respectively. The geometrical leakage current contribution shifts from the perimeter to the bulk as the diode sizes increase. Extracted near midgap activation energies are similar to p+/n Ge junctions formed by ion implantation. This indicates that the reverse leakage current in p+/n Ge diodes fabricated with various doping methods, could originate from the same trap-assisted mechanism. Working p+/n diodes on Ge bulk substrates displayed a reverse current density as low as 2.2·10−2 A/cm2 which was found to be comparable to other literature data. The layers developed in this work can be used as an alternative method to form p+/n junctions on Ge substrates, showing comparable junction leakage results to ion implantation approaches.

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“…Further, various researches have revealed that a miniaturized device in nanoscale may encounter the stress-strain impact on its electrical performance. [41][42][43][44][45][46][47][48][49][50][51][52][53] In this regard, the basic structure of a VSTB FET also indubitably exerts heavy stress over the thin vertical body as it is surrounded by thick dielectric walls and other parts of the device. Therefore, the study of the stress-strain influence on the performance of a VSTB FET is an integral part of its reliability establishment.…”

mentioning

confidence: 99%

Silicon and Germanium Vertical Super-Thin Body (VSTB) FET: A Comparative Performance Overview Including Architectural Stress-Strain Impact

Barman

Baishya

2022

ECS J. Solid State Sci. Technol.

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This article aims to develop a comprehensive understanding of the comparative performance of a vertical super-thin body (VSTB) field-effect transistor in terms of two device material variations (silicon/Si and germanium/Ge) with the aid of 3-D Senaturus TCAD tool. More importantly, the influence of the inevitable architectural stress (exerted over the thin body by the thick dielectric walls) on the transfer characteristic of the device is also addressed for Si/Ge device. From the perspective of suitability in high-performance circuits, Ge outperforms Si by enhancing on-state current (Ion) by 30.28, 30.29, 29.91, and 26.98 µA at channel length of 10, 20, 30, and 40 nm, respectively, with an improvable deterioration in off-state leakage current, subthreshold swing, and drain-induced-barrier-lowering. Further, a three-dimensional stress analysis reveals that stress increases Ion more in Ge-device compared to its Si-counterpart. As expected, a similar nature is observed for the strain application. Finally, the radio-frequency study shows that although the relative performance of Ge with respect to Si in terms of input capacitance, gate-drain capacitance, and output conductance is inferior, the greater transconductance of Ge than Si lowers intrinsic delay and enhances the peaks of intrinsic gain, unit-gain cut-off frequency, and gain-bandwidth-product.

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Investigation of process induced stress in the channel of a SiGe embedded source/drain Ge-FinFET architecture

Cited by 4 publications

References 25 publications

Narrowed Si_0.7Ge_0.3 channel FinFET with subthreshold swing of 64 mV/Dec using cyclic self-limited oxidation and removal process

Narrowed Si_0.7Ge_0.3 channel FinFET with subthreshold swing of 64 mV/Dec using cyclic self-limited oxidation and removal process

Selective Epitaxial Growth of In Situ Doped SiGe on Bulk Ge for p+/n Junction Formation

Silicon and Germanium Vertical Super-Thin Body (VSTB) FET: A Comparative Performance Overview Including Architectural Stress-Strain Impact

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Investigation of process induced stress in the channel of a SiGe embedded source/drain Ge-FinFET architecture

Cited by 4 publications

References 25 publications

Narrowed Si0.7Ge0.3 channel FinFET with subthreshold swing of 64 mV/Dec using cyclic self-limited oxidation and removal process

Narrowed Si0.7Ge0.3 channel FinFET with subthreshold swing of 64 mV/Dec using cyclic self-limited oxidation and removal process

Selective Epitaxial Growth of In Situ Doped SiGe on Bulk Ge for p+/n Junction Formation

Silicon and Germanium Vertical Super-Thin Body (VSTB) FET: A Comparative Performance Overview Including Architectural Stress-Strain Impact

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Narrowed Si_0.7Ge_0.3 channel FinFET with subthreshold swing of 64 mV/Dec using cyclic self-limited oxidation and removal process

Narrowed Si_0.7Ge_0.3 channel FinFET with subthreshold swing of 64 mV/Dec using cyclic self-limited oxidation and removal process