Investigation of Polysilazane-Based $\hbox{SiO}_{2}$  Gate Insulator for Oxide Semiconductor Thin-Film Transistors

Tu, Huynh Thi Cam; Inoue, Satoshi; Tue, Phan Trong; Miyasako, Takaaki; Shimoda, Tatsuya

doi:10.1109/ted.2013.2241440

Cited by 9 publications

(13 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The decrease in the dielectric constant with annealing temperature is possibly due to the oxidation of the PHPS in ambient condition while annealing [20] and breaking of the SiH, NH, or SiN bonds and re-bonding to form SiOH or SiO bonds in the annealed PHPS. The formation of SiO 2 from the SiON x as confirmed by the XPS data and Tu et al as the annealing temperature increases [16] confirm the reduction of the dielectric constant since SiO 2 has a lower dielectric constant compared to SiON x .…”

Section: Annealing Effect Of the Perhydropolysilazane (Phps)mentioning

confidence: 55%

“…This negatively shifts the transfer curves of the CTM PHPS@RT and CTM PHPS@100 °C further beyond the initial transfer curves (with no gate-bias) as seen in Figure 3b,c. Moreover, the reduction of the negatively charged nitrogen defects from the evaporated NH 3 after applying a higher annealing temperature over 250 °C [16] greatly affects the proton affinity or hole trap sites [40,41] within the PHPS. This limits the PHPS within the CTM-PHPS@450 °C to only electron traps with no hole trapping effect as seen in Figure 3d.…”

Section: Proposed Band Diagram Model For Pdpp4tand Igzo-based Ctmsmentioning

confidence: 99%

“…Notwithstanding, the underlying CTL dielectrics should withstand high temperatures since some of the solution-processed semiconductors such as metal oxide-based semiconductors require high annealing process temperatures to enhance the film quality. Tu et al used a solution-processed perhydropolysilazane ([H 2 Si-NH] n ) as gate insulator for oxide transistors [16] and showed the possibility of good insulating properties especially coupled with SiO 2 . The perhydropolysilazane (PHPS) is a chemical compound consisting of silicon as the main backbone with hydrogen and nitrogen elements which undergo chemical reactions when the annealing temperature increases.…”

mentioning

confidence: 99%

See 2 more Smart Citations

Perhydropolysilazane Charge‐Trap Layer in Solution‐Processed Organic and Oxide Memory Thin‐Film Transistors

Boampong

Lee

et al. 2022

Adv Elect Materials

View full text Add to dashboard Cite

The charge trapping property of spin‐coated perhydropolysilazane (PHPS) layers for solution‐processed organic and oxide thin film memory transistors is demonstrated. The nitrogen content within the PHPS layer is decreased by increasing the annealing temperatures from room temperature to 450 °C. The PHPS layer added to the SiO2 gate insulator in the charge trap memories (CTMs) shows good memory functionalities which are electrically programmable, and is erased either electrically or optically depending on the semiconductor used. The stored or erased charges in the p‐type semiconductor‐based CTM result in relatively large threshold voltage shifts (∆VTH > 60 V) and large memory on‐ and off‐current ratio (IM,ON/IM,OFF > 103) with the respective memory output current extrapolated to 108 s. The n‐type CTM shows ∆VTH ≈ 20 V, IM,ON/IM,OFF of 0.5 × 103 and is extrapolated to 1015 s. It is concluded that the origin of the charge‐traps in both the p‐type and n‐type CTMs mainly originates from the PHPS charge trap layer (CTL) and greatly occurs in highly concentrated nitrogen PHPS layers. There is a high possibility of using the PHPS CTL in a wide variety of cost‐effective CTMs even with high temperature processed semiconductors.

show abstract

Section: Annealing Effect Of the Perhydropolysilazane (Phps)mentioning

confidence: 55%

Section: Proposed Band Diagram Model For Pdpp4tand Igzo-based Ctmsmentioning

confidence: 99%

mentioning

confidence: 99%

See 1 more Smart Citation

Perhydropolysilazane Charge‐Trap Layer in Solution‐Processed Organic and Oxide Memory Thin‐Film Transistors

Boampong

Lee

et al. 2022

Adv Elect Materials

View full text Add to dashboard Cite

show abstract

“…We previously confirmed that the use of polysilazane‐based SiO 2 enables the fabrication of high‐density and high‐quality metal‐oxide semiconductor (MOS) interfaces . The polysilazane solution was spin‐coated and dried at 250 °C for 5 min.…”

Section: Tft‐epd Fabricationmentioning

confidence: 82%

Electrophoretic displays driven by all‐oxide thin‐film transistor backplanes fabricated using a solution process

Inoue

Phan

Hori

et al. 2015

Physica Status Solidi (a)

Self Cite

View full text Add to dashboard Cite

Precursor solutions and a solution process were developed for the fabrication of amorphous oxide thin-film transistors (TFTs). All the layers of the TFTs comprised oxide films prepared from precursor solutions. The gate lines, gate insulator, and channel layer comprised ruthenium oxide, lanthanum zirconium oxide, and zirconium indium zinc oxide films. The polysilazane-based silicon dioxide film was used for the channel stopper layer. The source-line and drain electrode had a double-layer structure comprising indium tin oxide and ruthenium oxide films. The silsesquioxane-based silicon dioxide and ruthenium oxide films were used for the passivation layer and pixel electrodes, respectively. The TFTs exhibited a field effect mobility of 2.68 cm 2 V À1 s À1 , a sub-threshold swing of 1.09 V/decade, a threshold voltage of 3.06 V, and an on/off ratio of 10 5 . Active-matrix electrophoretic displays (EPDs) with a resolution of 101.6 ppi were successfully fabricated using the all-solution-processed TFTs. Bi-stable black/ white images were confirmed in these TFT-EPDs for the first time.

show abstract

“…First, a ZrInZnO precursor solution was spin-coated onto a SiO 2 /Si substrate twice at 3000 rpm for 30 s and annealed by rapid thermal annealing (RTA) at 500 °C for 10 min in ambient oxygen to form a 40-nm-thick ZrInZnO film 16,17 4 ] dissolved in propionic acid. The atomic ratio of Zr:In:Zn was 0.1:2:1.…”

Section: Characteristics Of Sn-diffused Zrinzno Filmsmentioning

confidence: 99%

P‐1: Distinguished Poster: Fabrication of a Self‐Aligned ZrInZnO Thin‐Film Transistor Using Polypropylene Carbonate Solution

Inoue

Nishioka

et al. 2014

Symp Digest of Tech Papers

Self Cite

View full text Add to dashboard Cite

To fabricate a self‐aligned oxide semiconductor thin‐film transistor (TFT) using a solution process, we developed a novel diffusion method to dope ZrInZnO source and drain regions. In this method, Sn was allowed to diffuse into ZrInZnO from a solution of Sn mixed with polypropylene carbonate. The sheet resistance of the Sn‐containing ZrInZnO was reduced dramatically from 1 MΩ/□ to 6.8 KΩ/□. The self‐aligned ZrInZnO TFT exhibited a mobility of 20 cm2•V−1•s−1, a threshold voltage of 1 V, a subthreshold swing of 0.2 V/decade, and an on‐to‐off current ratio of 7.

show abstract

Investigation of Polysilazane-Based $\hbox{SiO}_{2}$ Gate Insulator for Oxide Semiconductor Thin-Film Transistors

Cited by 9 publications

References 19 publications

Perhydropolysilazane Charge‐Trap Layer in Solution‐Processed Organic and Oxide Memory Thin‐Film Transistors

Perhydropolysilazane Charge‐Trap Layer in Solution‐Processed Organic and Oxide Memory Thin‐Film Transistors

Electrophoretic displays driven by all‐oxide thin‐film transistor backplanes fabricated using a solution process

P‐1: Distinguished Poster: Fabrication of a Self‐Aligned ZrInZnO Thin‐Film Transistor Using Polypropylene Carbonate Solution

Contact Info

Product

Resources

About