Investigation of low-temperature deposition high-uniformity coverage Parylene-HT as a dielectric layer for 3D interconnection

Developing a leading practical application for 3D IC chip stacking technology

“…The specific items include the following. Elemental technologies for chip stacking process are the following: low-volume, lowresistance, and low internal stress TSV structure using low-k organic insulator; [17] micro-pitch, high-density, and micro-bump connection formed by a thermo-compression method using cone-shaped micro-bumps; [18]- [20] electroless plating connection for power source pads where the power source pad electrodes are connected by direct Ni-B and Au electroless plating after chip stacking; [21] [22] interposer with passive components where the thin film capacitors or the chip capacitors are embedded in the substrate; [23] [24] and others. Evaluation and inspection technologies are as follows: evaluation of electrical property in local fine structures using high-speed sharp step signals with 10-ps rising time; [25] evaluation of 20 Gbps high-speed digital signal transmission; [26] evaluation of power supply wiring impedance using impedance analyzer for 10 Hz -40 GHz super-wide bandwidth; [27] inspection of good chips where electrical testing can be done at chip level using the membrane fine pitch contact probe; [28] boundary scan embedded test circuit where total electrical connection test of fine interconnects can be conducted after stacking; [29] high-speed inspection of coneshape micro-bumps where wafer level shape optical inspection can be conducted by laser illumination and high-speed highresolution image sensors; [30] and others.…”

“…As an example of the development of a low-volume, lowresistance, and low internal stress TSV structure, we describe the development of a TSV structure using the parylene organic resin as the insulating layer of the TSV sidewall. [17] Figure 5 shows the manufacturing process flow of the TSV structure with parylene sidewall insulating layer, where the uniform parylene thin film was formed using low-temperature CVD method. Figure 6 shows the crosssectional SEM photograph after the formation of a parylene sidewall insulating layer in the TSV manufacturing process.…”

Reactive Sputtered Silicon Nitride as an Alternative Passivation Layer for Microelectrode Arrays in Sensitive Bioimpedimetric Cell Monitoring

“…The application of polymer-based channel structures (e.g., PEGDA or PDMS) often leads to adhesion problems and leakages because SU8 swells in a humid environment, and thus the adhesion of polymers on the SU8 surface is critical . Alternative organic polymer-based coatings to insulate the conducting paths can be achieved by polyimides, which can be processed as a photosensitive liquid polymer similar to SU8, − or different types of parylene (parylene-N, -C, or -HT), which are produced by vacuum polymerization. − In general, a major advantage of organic polymer-based passivation coatings is a lower dielectric constant compared to sputtered inorganic passivation layers. Among inorganic passivation materials, the most common are silicon compounds such as silicon oxide (SiO 2 ) , and non-oxide ceramics such as silicon nitride (SiN), , which are applied as single-layer or sandwich chemical vapor deposition (CVD) coatings named ONO layers.…”

A method enabling height-control of chips for edge-emitting laser stacking

“…In our previous works, we have succeeded in demonstrating of reliable Au microbump interconnections with submicron range bonding accuracy. The conventional bonding bump and pad elements have been appropriately modified to construct a concave-convex pair, i.e., self-aligned intercon- nection elements (SIEs), [15][16][17][18][19][20][21] for having highly reproducible submicron range bonding precision in the x-and y-axes. Moreover, with this bonding approach, bonding height could be determined during the bonding period through the applied bonding forces [Fig.…”