Investigation of charge loss mechanisms in planar and raised STI charge trapping flash memories

Abstract

A comprehensive simulation to investigate the charge loss mechanisms in planar and raised STI NAND-type charge trapping flash (CTF) memories with careful calibrations is present. The tunneling and silicon nitride trap transport with Poole-Frenkel (PF) effect are solved selfconsistently and validated based on the experimental data including gate stacks leakage, program speed, and high temperature retention. Based on the programmed state, the high temperature retention is simulated and compared with the measurement data. In planar CTF, the vertical charge loss through tunneling layers and blocking layers are analyzed. The results show that the former is the dominant one. Finally, the charge loss in raised STI CTF is compared with that in planar CTF. The results show that the enhanced charge loss in raised STI CTF is induced by the lateral spreading and the non-uniform charge storage nearby the STI edge, especially in the narrow width (100nm) raised STI CTF.

Numerical simulation of vertical tunnelling field-effect transistors charge-trapping memory with TCAD tools

“…The data retention characteristics were closely related to the dielectric layer thickness in the Flash device [34,35]. To investigate the T oxb and T SiN thickness influence on the retention characteristics, the variable was set as ±25% with a step of 5% in the simulation.…”

“…In table 3 a comparison is made for the VT-SONOS NVM with the recently reported poly-Si channel SONOS NVMs [32][33][34][35][36][37][38][39]. Under the FN programming conditions, the VT-SONOS showed an MW of 2.95 V when the gate pulse width was 2.5 ms. Its performance is superior as we can achieve SS (102.09 mV dec −1 ) and I ON (3.02 × 10 −4 A), which was better than those of recently developed high-quality memory.…”

Advancements in Complementary Metal-Oxide Semiconductor-Compatible Tunnel Barrier Engineered Charge-Trapping Synaptic Transistors for Bio-Inspired Neural Networks in Harsh Environments

“…Particularly at elevated temperatures, even a few stimulus pulses yielded rapid EPSC escalation. This phenomenon occurs because the charges trapped within the CTL require less energy to tunnel via the VARIOT tunnel barrier under high-temperature conditions [32,33]. The conventional learning/memory mechanism proposed by Atkinson and Shiffrin for biological neural systems underscores the transition from STM to LTM via stimulus rehearsal.…”