Investigation of Band-Gap Engineered Silicon-Oxide-Nitride-Oxide-Silicon Flash Memory with High-k Dielectrics in Tunnel Barrier and Its Impact on Charge Retention Dynamics

Optimization of high-k composite dielectric materials of variable oxide thickness tunnel barrier for nonvolatile memory

“…The primary purpose of VARIOT optimization work has been divided into two objectives: 1) To simulate and determine the optimum set of dielectric material combination, the equivalent oxide thickness (EOT), the optimum thickness of low-k (Tox) dielectric layer for minimum programming voltage (Vprog) and 2) To extract F-N tunneling coefficients of the optimum asymmetric stack. The equivalent oxide thickness (EOT) and optimum thickness of low-k (Tox) are determined for each combination of the asymmetric stack (low-k/high-k) in which satisfying program, retention and read-disturb constraints of flash memory using the method proposed by Verma et al (2010) [7]. Thus, the optimum combination of the asymmetric stack is selected based on minimum programming voltage (Vprog).…”

“…In order to optimize these parameters, there are two things need to be clarified. Firstly, the high-k materials of the asymmetric stacks need to be chosen based on their criteria [7][8]. One of the critical criteria is the materials can be deposited on the SiO2 layer.…”

“…Beforehand, the concept of Crested Barrier Engineering first is introduced by Likharev et al in 1999 [6]. Few reports stated that TBE stack has a higher field-sensitivity compared to the single SiO2 layer which allows shorter P/E time, smaller operating voltage plus the ten (10) years retention time is not affected [2,7]. Also, it was stated that different dielectric materials would exhibit different performance of the device performance as their properties are different each other [7][8].…”

“…Few reports stated that TBE stack has a higher field-sensitivity compared to the single SiO2 layer which allows shorter P/E time, smaller operating voltage plus the ten (10) years retention time is not affected [2,7]. Also, it was stated that different dielectric materials would exhibit different performance of the device performance as their properties are different each other [7][8]. Driussi et al (2005) have conducted theoretical analysis on the performance of Crested Barrier and VARIOT concept as resulting that the VARIOT combinations yield better performance than Crested Barrier combinations in terms of low operating voltage and better retention.…”

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

“…[3][4][5][6][7]10) In addition, it also suffers from poor retention due to the charge-trapped around the triangular corners. To compensate both the programming time and data retention of GAA-FG, in this work, the tunnel barrier engineering concept of variable oxide thickness (VARIOT) [11][12][13][14][15][16] as tunnel layer is utilized. It has been previously studied for charge-trapping 15,16) and even for hybrid floating [17][18][19] gate devices and its performances as tunnel oxide layer for 3D FG cell is yet to be unveiled.…”