Investigation into the capabilities of Hall cells integrated in a non-fully depleted SOI CMOS technological process

Paun, Maria‐Alexandra; Udrea, F.

doi:10.1016/j.sna.2016.02.014

Cited by 5 publications

(3 citation statements)

References 18 publications

(25 reference statements)

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“…The process reported here involves commercial chips based on the XI10 technology available from X-FAB Semiconductor Foundries, which uses 1-μm design rules in a partially depleted SOI CMOS process originally designed for applications that demand stable operation at high temperatures (37,38). Completed 6-inch wafers, as shown in Fig.…”

Section: Resultsmentioning

confidence: 99%

Materials and processing approaches for foundry-compatible transient electronics

Chang

Fang

Bower³

et al. 2017

Proc. Natl. Acad. Sci. U.S.A.

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Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for "green" electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-theart silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are (i) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, (ii) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and (iii) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries.soft electronics | biodegradable electronics | transfer printing | undercut etching | hydrolysis S emiconductor technology is increasingly essential to nearly all aspects of modern society, with projections of market sizes that will exceed $7 trillion in 2017, equivalent to 10% of the world's gross domestic product (1-4). The rapid and accelerating pace of innovation in this area leads to increases in the frequency with which consumers upgrade their devices, thereby contributing to the production of >50 million tons of electronic waste (e-waste) each year (5, 6). Furthermore, the anticipated emergence of electronics for internet-of-things applications, along with the continued proliferation of radio frequency (RF) identification tags and other high-volume electronic goods, create daunting challenges with the management of this e-waste (7, 8). These considerations motivate research into forms of electronics that can degrade naturally into the environment to harmless end products. Such technology is also of interest for other, unique classes of applications, ranging from biodegradable, temporary electronic implants to hardware secure data systems and unrecoverable, field-deployed devices (9-12). Sometimes referred to collectively as transient electronics, these types of devices can be constructed by using designer materials, such as specially formulated polymers or natural products (13-16), or clever combinations of established materials, well-aligned to existing ...

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Section: Resultsmentioning

confidence: 99%

Materials and processing approaches for foundry-compatible transient electronics

Chang

Fang

Bower³

et al. 2017

Proc. Natl. Acad. Sci. U.S.A.

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“…Several existing studies have investigated the temperature and power performances of SOI Hall sensors via experimental methods [ 8 , 9 ]. Some research has also adopted three-dimensional (3D) physical models to simulate the design optimization of SOI Hall cells [ 10 , 11 , 12 , 13 ]. Dolgyi et al [ 10 ] studied the dependencies of electric characteristics on the process parameters of SOI Hall sensors.…”

Section: Introductionmentioning

confidence: 99%

“…However, this research was limited to the analysis of electrical characteristics, such as current-voltage characteristics, the threshold voltage, and the breakdown voltage, and presented less discussion on the effects of bias, geometries, or other design parameters on sensitivity, offset voltage, and power consumption. Paun et al [ 13 ] analyzed the behavior of an optimum Hall cell in a partially depleted SOI (PD-SOI) fabrication process by constructing a 3D physical model of the structure and performing simulations; however, the SOI Hall sensor structure in this work did not use the FD state, and an analysis of gate and substrate voltage regulation was absent.…”

Section: Introductionmentioning

confidence: 99%

Performance Optimization of FD-SOI Hall Sensors Via 3D TCAD Simulations

Fan

et al. 2020

Sensors

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This work investigates the behavior of fully depleted silicon-on-insulator (FD-SOI) Hall sensors with an emphasis on their physical parameters, namely the aspect ratio, doping concentration, and thicknesses. Via 3D-technology computer aided design (TCAD) simulations with a galvanomagnetic transport model, the performances of the Hall voltage, sensitivity, efficiency, offset voltage, and temperature characteristics are evaluated. The optimal structure of the sensor in the simulation has a sensitivity of 86.5 mV/T and an efficiency of 218.9 V/WT at the bias voltage of 5 V. In addition, the effects of bias, such as the gate voltage and substrate voltage, on performance are also simulated and analyzed. Optimal structure and bias design rules are proposed, as are some adjustable trade-offs that can be chosen by designers to meet their own Hall sensor requirements.

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Effects of Temperature, Thickness and Bias Current on Magnetoelectric Characteristics of Silicon Micro-Hall Sensors

Akram

2018

Arab J Sci Eng

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Investigation into the capabilities of Hall cells integrated in a non-fully depleted SOI CMOS technological process

Cited by 5 publications

References 18 publications

Materials and processing approaches for foundry-compatible transient electronics

Materials and processing approaches for foundry-compatible transient electronics

Performance Optimization of FD-SOI Hall Sensors Via 3D TCAD Simulations

Effects of Temperature, Thickness and Bias Current on Magnetoelectric Characteristics of Silicon Micro-Hall Sensors

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