Investigation into micropipeline latch design styles

Abstract

An asynchronous implementation of the ARM microprocessor has been designed and fabricated based on Sutherland's Micropipeline approach. Reviews of this work have shown that considerable performance improvement may be possible in a number of key design areas. This paper assesses the effects of different design styles on the micropipeline latch structures used. The original design has latch structures based on passtransistor transparent latches. An evaluation of the use of single-phase transparent latch structures is given plus the application of 2-phase and 4-phase control techniques.

The Family of 4-phase Latch Protocols

“…Certain protocols can only store data in every other latch when the pipeline is stalled 3 , called half-buffering [8]. Any protocol that does not contain the state marked with × in Figure 4 (or that remove any states in R2) cannot store data in every latch when stalled.…”

“…Thus such structured pipelines may be thinned or fattened with no effect visible to the external observer of their control signals. This is a very useful guarantee and a handy simplification when 3 Assuming pulse latch clocking is not employed. …”

Practical advances in asynchronous design and in asynchronous/synchronous interfaces

“…There has been a tremendous amount in asynchronous pipelines, starting with the classical micropipeline work by Sutherland [63]. Pipeline control can be implemented using either a two-phase protocol [24,76,1] or a four-phase protocol [19,28,25,27].…”

Fourteen ways to fool your synchronizer

“…A fourphase protocol is specified by means of a generalized STG in Figure 2, where "DD" means that the data is available (at the sender), "UU" means that it may be removed, and "LL" means data latched by the receiver. (A two-phase protocol may also be employed; the circuits are a bit more complex [13,14], and this is typically used in order to minimize latency on long lines.) The complete logic and FSM are shown in Figure 3.…”