Investigating the Reasons for the Difficult Erase Operation of a Charge‐Trap Flash Memory Device with Amorphous Oxide Semiconductor Thin‐Film Channel Layers

Abstract

A charge‐trap flash (CTF) device is fabricated using atomic‐layer‐deposited zinc tin oxide (ZTO) as an n‐type amorphous oxide semiconductor (AOS) channel layer and its program/erase characteristics are examined. When a positive voltage of 20 V is applied to the gate electrode, electrons are fluently injected into the adopted SiNx charge trap layer, resulting in a program operation showing a threshold voltage (Vth) shift of 3.7 V. However, even when −20 V is applied for up to 10 s, the trapped electrons are not detrapped. Instead, it is possible to recover Vth to its initial value only by the irradiation of white light. To understand this phenomenon, a ZTO CTF device is modeled using the technology computer‐aided design (TCAD) simulation package. The high hole injection barrier between the source/drain and the ZTO channel prohibits hole injection, which is the cause of the inefficient erasing. It is also confirmed that an AOS CTF with sufficient program and erase speed would be limited by the inherent energy band structure of AOS with its wide bandgap of over 3 eV. An alternative method of using the fringing field effect according to channel length scaling is proposed.

Effect of Gate Bias Stress on the Electrical Characteristics of Ferroelectric Oxide Thin-Film Transistors with Poly(Vinylidenefluoride-Trifluoroethylene)

“…Moreover, the trapped electrons hinder the charge accumulation for channel formation, which further shifts the V T and transfer curve in the positive direction ( Figure S2, Supplementary Materials ). Under NBS, a small electric field is applied to the gate insulator due to depletion of IGZO during NBS, resulting in only a small or negligible negative shift [ 21 , 22 ]. Therefore, with dielectric gate insulators, both bottom- and top-gate OxTFT show conventional transfer curve shift by GBS.…”

Synaptic Transistor Based on In‐Ga‐Zn‐O Channel and Trap Layers with Highly Linear Conductance Modulation for Neuromorphic Computing

“…[24,25] Among them, the charge trapping-based synaptic transistor has the advantages of high stability and CMOS compatibility. [26] However, the low efficiency of charge de-trapping caused by difficult hole injection, as previously reported in the IGZO-based charge trap memory, [27,28] prevents the increase in channel conductance, hindering weight modulation for implementing synaptic behaviors. Due to the wide Brain-inspired neuromorphic computing has drawn significant attraction as a promising technology beyond von Neumann architecture by using the parallel structure of synapses and neurons.…”

Review of Semiconductor Flash Memory Devices for Material and Process Issues

“…Hole h injection from the peripheral circuits is also highly inefficient due to their naturally high hole h barrier at the contact region. [130] High work function metal could be considered for better hole h injection, but that may incur the problem of a high electron barrier. [131] Also, the process integration issues, including the uniform film deposition of the multicomponent oxide with the deep hole c and other contamination control in the fabrication line, have not been sufficiently addressed yet.…”