Introduction to SRAM

Singh, Jawar; Mohanty, Saraju P.; Pradhan, Dhiraj K.

doi:10.1007/978-1-4614-0818-5_1

Cited by 8 publications

(8 citation statements)

References 28 publications

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“…Both the cells are analyzed for hold and read stability in terms of static noise margin (SNM). The SNM for a bit cell is defined as the maximum noise a bit cell can withstand before an error is registered by the cell [42]. The conventional method to determine the SNM for the bit cell is the butterfly curve [43].…”

Section: Perfromance Of Sa-p With a Single Ended Sram Bit Cellsmentioning

confidence: 99%

A latch-based sense amplifier with improved performance for single ended SRAM application

Rawat

Mittal

2023

Phys. Scr.

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The growing processing load and decreasing technology node has augmented the need for single ended memory. Consequently, generating requirement for a single ended sense amplifier for ease of integration with single ended memory. Therefore, this paper presents a single bitline based latch type sense amplifier. It is designed at feature size of 32 nm and its performance is evaluated at 1 V supply, with the environment temperature at 27 ⁰C. It is analyzed for its output waveform, delay, variability tolerance, and area occupancy. The ON current for the proposed sense amplifier is 1.2 uA, while the OFF current is 10 nA. The ON current for proposed sense amplifier is is 0.18, 0.43, and 0.88 times higher than SA-2, SA-5, and SA-6 respectively. While, its OFF current is lowest with the exception of SA-3 at 9 nA. Also, the delay for the proposed sense amplifier is minimal at 0.77 ns in comparison to other topologies. The SA-1, SA-2, SA-5, and SA-6 are 3.9, 2.8, 3.7, and 0.3 times slower than SA-P, thereby deeming its operation faster than others. The reliability for the proposed circuit is evaluated using process corner analysis for all performance parameters.

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Section: Perfromance Of Sa-p With a Single Ended Sram Bit Cellsmentioning

confidence: 99%

A latch-based sense amplifier with improved performance for single ended SRAM application

Rawat

Mittal

2023

Phys. Scr.

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“…A SRAM bit cell with such a read configuration has its read static noise margin(RSNM) equivalent to its hold static noise margin (HSNM) [27]. This read port configuration is also referred to as isolated read with a read free noise margin [41].…”

Section: Read Operationmentioning

confidence: 99%

“…The RSNM and HSNM for each bit cell are measured using the butterfly curve, obtained by superimposing the voltage transfer characteristics for the bit cell during the hold and read modes, respectively. The side of the square inside the lobe of the butterfly curve is taken as the measure of SNM [41]. The butterfly curves for the RSNM and HSNM for the proposed SRAM bit cell overlap and are shown in figure 3(a).…”

Section: Static Analysismentioning

confidence: 99%

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A 32 nm single-ended single-port 7T static random access memory for low power utilization

Rawat¹,

Mittal²

2021

Semicond. Sci. Technol.

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In this paper, a seven-transistor static random access memory (SRAM) bit cell with a single bitline architecture is proposed. This cell is designed at 32 nm and is operational at 300 mV. The static noise margin for the read and hold modes is 90 mV, while the write margin is 180 mV. Monte Carlo analysis for 6σ global variations and temperature variation analysis for temperatures in the range −10 • C to 80 • C validate its performance. The cell is compared with other single-ended 5T, 6T, 7T, 8T, 9T and 10T SRAM cells and is found to be superior in performance. As the leakage current is low, the I ON /I OFF ratio is high compared with the other cells. The power consumption of the bit cell is also found to be minimal for all modes of operation. The dynamic write analysis demonstrates that the proposed cell completes the write operation in a 10 ns pulse width. Moreover, the improvement in performance is obtained for an area as low as 0.539 µm 2 . The area of 5T, 6T, 7T-1, 7T-2, 7T-4, 7T-5, 8T, 9T and 10T cells is greater than the 7TP bit cell area by 22.

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“…In [9], an SRAM cell with four loadless transistors, in [25], a cell with four transistors based on polysilicon resistance, in [10], a cell with five transistors, in [26] and [12], cells with six, seven, and ten transistors, and in [27], cells with ten transistors based on Schmidt trigger have been proposed.…”

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confidence: 99%

A novel design of high performance and robust ultra-low power SRAM cell based on memcapacitor

Abbasi¹,

Setoudeh²,

Tavakoli³

et al. 2022

Nanotechnology

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The present paper proposes a six-FinFET two-memcapacitor (6T2MC) non-volatile static random-access memory (NVSRAM). In this design, the two memcapacitors are used as non-volatile memory elements. The proposed cell is flexible against data loss when turned off and offers significant improvement in read and write operations compared to previous NVSRAMs. The performance of the new NVSRAM design is evaluated in terms of read and write operation at particular nanometric feature sizes. Moreover, the proposed 6T2MC cell is compared with 8T2R, 8T1R, 7T1R, and 7T2R cells. The results show that 6T2MC has a 5.50% lower write delay and 98.35% lower read delay compared to 7T2R and 7T1R cells, respectively. The 6T2MC cell exhibits 38.86% lower power consumption and 23.80% lower leakage power than 7T2R and 7T1R cells. The proposed cell is significantly improved in terms of HSNM, RSNM, and WSNM compared to 8T2R, 8T1R, 7T2R, and 7T1R cells, respectively. Important cell parameters, such as power consumption, data read/write delay, and SNM, are significantly improved. The superior characteristics of FinFET over MOSFET and the combination of this technology with memcapacitors lead to significant improvement in the proposed design.

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Introduction to SRAM

Cited by 8 publications

References 28 publications

A latch-based sense amplifier with improved performance for single ended SRAM application

A latch-based sense amplifier with improved performance for single ended SRAM application

A 32 nm single-ended single-port 7T static random access memory for low power utilization

A novel design of high performance and robust ultra-low power SRAM cell based on memcapacitor

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