Introduction To BiCMOS

Alvarez, A.R.

doi:10.1007/978-1-4757-2029-7_1

Cited by 10 publications

(3 citation statements)

References 21 publications

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“…The reason for the higher gain is that BJTs transconductance is directly proportional to the DC current of the collector, while CMOS transconductance is proportional to the square root of the drain DC current [8]. Hence, for the same current, BJT transistors have much higher transconductance than MOS transistors, which translates into higher gain, speed and lower noise [2], [9]. BJT, on the other hand, has smaller input resistance and larger input current thereby demanding much higher power consumption.…”

Section: A Input Buffermentioning

confidence: 99%

A case for 3D stacked analog circuits in high-speed sensing systems

Abdel-Majeed

Chen

Annavaram

2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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In order to build high performance real-time sensing systems every building block in the system should be built with a technology that allows that building block to achieve its best performance. Technologies like BJT and BICMOS are better suited for building basic analog blocks like input buffers and power amplifiers, while CMOS is the best choice for digital data processing. To build mixed-technology systems traditionally system-in-package (SiP) techniques are used. SiP integration uses bonding wires or flip chip instead of on-chip integration. In this paper we study the feasibility of using 3D stacking to integrate heterogeneous blocks built using different technologies within a real-time sensing system. Several of the previous studies on 3D stacking focused on integrating multiple digital blocks and using through-silicon-vias (TSVs) to transfer digital signals between the layers in a stack. In this paper we study the behavior of the analog signals traversing through TSVs and measure how well 3D stacking can enhance or limit the performance of analog and digital stacking. In order to quantify the power and performance characteristics, we modeled bonding wire, flip chip, and through-silicon-via (TSV) interfaces. Using these models we show that 3D stacking of analog and analog/digital components can double the bandwidth, increase sampling frequency by nearly two orders magnitude and and improve the signal integrity by 3 dB compared to bond wires.

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Section: A Input Buffermentioning

confidence: 99%

A case for 3D stacked analog circuits in high-speed sensing systems

Abdel-Majeed

Chen

Annavaram

2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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“…The latter is relatively more complex than the limited swing version [5]. However scaled down technologies using lower supply voltages requires another type of BiCMOS circuit configuration.…”

Section: Basic Circuitsmentioning

confidence: 99%

Testability analysis and fault modeling of BiCMOS circuits

1992

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Defect models have been used for testability analysis of BiCMOS circuits and the results have been compared with an analysis of CMOS circuits. Using a nominal point approach, faults generated are classified as logical or performance degradation faults. It is found that logical fault testing can only cover a small percentage of the total fault set, 54% for BiCMOS, versus 69% for equivalent CMOS gates. Delay faults and current faults are analyzed as applied to BiCMOS and CMOS gates. It is shown that logical fault testing in conjunction with either delay fault testing or current fault testing promises the highest fault coverage for BiCMOS logic gates, around 95%.

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“…BiCMOS technology, which is a combination of bipolar technology and CMOS technology, was developed to achieve complementary advantages from both technologies and thus offer lower power dissipation, and better gain and current driving capability on the same Si chip. 3,4 As a result, BiCMOS technology has been widely used in logic circuits and particularly mixed-signal systems [5][6][7][8] in electronics industry for the last two decades or so.…”

Section: Introductionmentioning

confidence: 99%

High-performance flexible BiCMOS electronics based on single-crystal Si nanomembrane

et al. 2017

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In this work, we have demonstrated for the first time integrated flexible bipolar-complementary metal-oxide-semiconductor (BiCMOS) thin-film transistors (TFTs) based on a transferable single crystalline Si nanomembrane (Si NM) on a single piece of bendable plastic substrate. The n-channel, p-channel metal-oxide semiconductor field-effect transistors (N-MOSFETs & P-MOSFETs), and NPN bipolar junction transistors (BJTs) were realized together on a 340-nm thick Si NM layer with minimized processing complexity at low cost for advanced flexible electronic applications. The fabrication process was simplified by thoughtfully arranging the sequence of necessary ion implantation steps with carefully selected energies, doses and anneal conditions, and by wisely combining some costly processing steps that are otherwise separately needed for all three types of transistors. All types of TFTs demonstrated excellent DC and radio-frequency (RF) characteristics and exhibited stable transconductance and current gain under bending conditions. Overall, Si NM-based flexible BiCMOS TFTs offer great promises for high-performance and multifunctional future flexible electronics applications and is expected to provide a much larger and more versatile platform to address a broader range of applications. Moreover, the flexible BiCMOS process proposed and demonstrated here is compatible with commercial microfabrication technology, making its adaptation to future commercial use straightforward.

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Introduction To BiCMOS

Cited by 10 publications

References 21 publications

A case for 3D stacked analog circuits in high-speed sensing systems

A case for 3D stacked analog circuits in high-speed sensing systems

Testability analysis and fault modeling of BiCMOS circuits

High-performance flexible BiCMOS electronics based on single-crystal Si nanomembrane

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