Defect models have been used for testability analysis of BiCMOS circuits and the results have been compared with an analysis of CMOS circuits. Using a nominal point approach, faults generated are classified as logical or performance degradation faults. It is found that logical fault testing can only cover a small percentage of the total fault set, 54% for BiCMOS, versus 69% for equivalent CMOS gates. Delay faults and current faults are analyzed as applied to BiCMOS and CMOS gates. It is shown that logical fault testing in conjunction with either delay fault testing or current fault testing promises the highest fault coverage for BiCMOS logic gates, around 95%.
Common defects are modelled for BiCMOS logic gates. Results suggest that common logical-fault testing methods would be less appropriate for BiCMOS gates than for the corresponding CMOS gates. However, results also indicate that, by applying logical-fault testing in combination with delay-fault testing. fault coverage should be increased to more acceptable levels. BACKGROUNDBiCMOS is a relatively recent integrated circuit fabrication technology that is becoming increasingly important to designers .BiCMOS devices benefit from most of the advantages of each technology, and few of the disadvantages. Relative to CMOS devices, they operate at very high speed, can drive large fan-outs, are relatively insensitive to ESD, allow simple level-conversion circuitry for external interfacing, and are virtually immune to latch-up PEF88J. Also, BiCMOS devices consume less power than purely-bipolar devices. Relative to CMOS, the main drawbacks include a slightly lesser packing density, a higher cost, and a longer fabrication time; the latter two of which are due to the added process complexity [ALV89].Thus, with all the advantages of BiCMOS, it should not be surprising that it is gaining in popularity, particularly for high-speed applications. However, since BiCMOS is an emergent technology, the body of knowledge with respect to its testability and fault modelling is indeed thin [DIAW]. Therefore, the purpose of this paper will be to address one important area, that of BiCMOS defect modelling and fault analysis.Since BiCMOS gates combine both CMOS and bipolar devices on the same substrate, they are subject to most of the defects from which each individual technology suffers. For the purposes of this paper, the following set of defects are modelled as representative of the majority of IC failure mechanisms [BUR88], [MENW]. The first two categories, gate-source or gate-drain pinholes, and gate-well pinholes, are caused by the same failure mechanism, a pinhole in the gate oxide of the MOS device.: Gate-Source or Gate-Drain PinholesThese defects, caused by pinholes in the gate-oxide, are modelled by a 1KQ resistor between the appropriate device terminals on the MOS devices WW851. Gate-Well PinholesA simplified model is employed here, primarily modelling the capacitive effect of a pinhole in the gate-oxide when such a pinhole occurs in the device's channel but outside of the drain or source region. The "gross" effect is modelled by decreasing the gate-oxide thickness by a factor of 50 from its nominal value. Emitter-Collector PipesThis defect is indigenous to bipolar devices and can be adequately modelled resistively by a 1KQ resistor between the transistor's collector and emitter terminals [TIM831 [BAR76]. Terminal ShortsThese defects are modelled by a simple connection between the two appropriate terminals. Terminal OpensA small 0.001 pF capacitor, in parallel with a lOGQ, resistor is inserted between the device terminal and the circuit node to which the terminal would otherwise be connected.CH 30064/91/0000 -2152 $1 .oO 0 IEEE
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