In this paper, a simple model for the estimation of static leakage current in NMOS transistor stacks is introduced. The three leakage mechanisms addressed are subthreshold leakage, gate-tunneling and gate induced drain leakage (GIDL). The algorithmic description of the model can be broken down into three phases i) pre-extraction , ii) estimation and iii) width scaling.In the pre-extraction phase, data necessary for subthreshold leakage estimation is extracted a priori. This also involves characterizing voltages required for a specific set of input vector scenarios (exception vectors/voltages). In the estimation phase, unit width GIDL and gate tunneling are estimated deterministically while subthreshold leakage is estimated using the pre-extracted data. Finally, in the width scaling phase each leakage component is then width scaled and summed, to give the total static leakage exhibited by the stack.The proposed model was scripted in MatLab and compared with SPICE simulations for various scenarios. The average total error for each scenario was under 3%.
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