Ditaduras: Memória, Violência E Silenciamento 2017
DOI: 10.7476/9788523220044.0001
|View full text |Cite
|
Sign up to set email alerts
|

Introdução

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1
1

Citation Types

0
2
0
4

Year Published

2017
2017
2023
2023

Publication Types

Select...
3
1

Relationship

0
4

Authors

Journals

citations
Cited by 4 publications
(8 citation statements)
references
References 0 publications
0
2
0
4
Order By: Relevance
“…In order to analyze a marked PN it is necessary to verify the good properties, such as: Reachability, Liveness and Boundedness [11][12][13]. The method proposed by [11][12][13] to verify the good properties is based on the analysis by markings enumeration, checking if the PN is limited by the reachability tree building and then the design of the accessible markings graph in order to validate if the graph is strongly connected, in other words if all the nodes in pairs are connected by a path is possible to evaluate if the PN is resettable which means that the PN is capable of recovering from disruptive operating events, such as: interruptions by the operator or by the safety device. The vivacity is evaluated when it is possible to access every part of the PN without any type of blockage [10].…”
Section: International Journal Of Advanced Engineering Research and Science (Ijaers)mentioning
confidence: 99%
See 1 more Smart Citation
“…In order to analyze a marked PN it is necessary to verify the good properties, such as: Reachability, Liveness and Boundedness [11][12][13]. The method proposed by [11][12][13] to verify the good properties is based on the analysis by markings enumeration, checking if the PN is limited by the reachability tree building and then the design of the accessible markings graph in order to validate if the graph is strongly connected, in other words if all the nodes in pairs are connected by a path is possible to evaluate if the PN is resettable which means that the PN is capable of recovering from disruptive operating events, such as: interruptions by the operator or by the safety device. The vivacity is evaluated when it is possible to access every part of the PN without any type of blockage [10].…”
Section: International Journal Of Advanced Engineering Research and Science (Ijaers)mentioning
confidence: 99%
“…In this way it is possible to state that this marked PN modeling of the automated test system for mobile phone battery is limited if it falls within the first good property, because if all the positions of a RP are k-bound, then the network is k-limited, being a safe PN if it is k-bounded with k = 1 according to [10]. Following the enumeration marking analysis , since the marked network is limited, the second and third part of the analysis is to build the accessible markings graph as shown in the figure 11, in order to verify and certify that the graph is strongly connected [13], since there is a path between the initial marking M0 and any marking Mj belonging to the graph vectors, in this way for all accessible markings there must be at least one tagged transition enabling the progress of the transition states. Thus, the marked PN has Liveness, since it is capable of recovering from operation disturbing events, such as interruptions by the operator or safety device [10] and also has a Boundedness characteristic, since all parts of the PN are accessible and it is ensured that there will be no blockage.…”
Section: Pn Development -Full Modelmentioning
confidence: 99%
“…Esta técnica admite a representação clara e compilada das funções e do desenvolvimento dos processos, proporcionando a caracterização da dinâmica do sistema, bem como a realização das táticas de controle. A rede de Petri é ideal para a caracterização de sistemas com processos concorrentes, não sincronizados, paralelos e distribuídos [9][10][11].…”
Section: Introductionunclassified
“…O nível mais baixo de abstração de um HDL é o estrutural, que consiste em uma representação do circuito semelhante a um netlist de portas lógicas ou de switches [35]. Esse nível de abstração é formado por dois subníveis: switches e unidades lógicas, respectivamente.…”
Section: Níveis De Abstração Hdlunclassified
“…Antes de descrever as fases do fluxo de projeto é necessário destacar que o conjunto de ferramentas de software associado a um fluxo de projeto provê ao desenvolvedor um nível de abstração que o permite focar no algoritmo a ser desenvolvido, ao invés de se preocupar com os circuitos que serão implementados. Dessa forma, a programação do dispositivo pode ser feita através de uma linguagem de programação (VHDL) ou mesmo através de modelagem de sistemas [35]. As empresas fabricantes de FPGA geralmente disponibilizam ferramentas para fazer a modelagem do sistema.…”
Section: Fluxo De Projeto Para Fpgaunclassified