2001
DOI: 10.1109/7298.946454
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Intrinsic reliability projections for a thin JVD silicon nitride gate dielectric in P-MOSFET

Abstract: Abstract-A comprehensive study of the intrinsic reliability of a 1.4-nm (equivalent oxide thickness) JVD Si 3 N 4 gate dielectric subjected to constant-voltage stress has been conducted. The stress leads to the generation of defects in the dielectric. As the result, the degradation in the threshold voltage, subthreshold swing, gate leakage current, and channel mobility has been observed. The change in each of these parameters as a function of stress time and stress voltage is studied. The data are used to proj… Show more

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Cited by 9 publications
(6 citation statements)
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“…5,6 The attempts to grow AlN on SiO 2 or Al 2 O 3 were encouraged by these results since the pure AlN films always show a thin Si 3 N 4 at the interface and the electrical properties probably are dominated by this Si 3 N 4 . The idea was to replace the interfacial layer and modify the interfacial and charging properties while maintaining the good leakage properties and high permittivity of the AlN.…”
Section: B Electron Mobilitymentioning
confidence: 94%
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“…5,6 The attempts to grow AlN on SiO 2 or Al 2 O 3 were encouraged by these results since the pure AlN films always show a thin Si 3 N 4 at the interface and the electrical properties probably are dominated by this Si 3 N 4 . The idea was to replace the interfacial layer and modify the interfacial and charging properties while maintaining the good leakage properties and high permittivity of the AlN.…”
Section: B Electron Mobilitymentioning
confidence: 94%
“…3,4 This study focuses on AlN which is a rather unexplored candidate as a gate dielectric, as are most other nitrides with the exception of Si 3 N 4 . 5,6 Past studies on using AlN as a gate dielectric for long channel FETs reported quite poor electrical properties, 7,8 e.g., a peak electron mobility at 40 cm 2 /V s. 7 In this work we report on a microstructural and electrical evaluation of AlN as a gate dielectric for Si based FETs. This includes mobility and charge trapping behavior as well as growth characteristics under different conditions and on various surfaces.…”
Section: Introductionmentioning
confidence: 98%
“…By controlling the initial bulk trap density, JVD MNSFETs can be expected to outperform MOSFETs. Scaling Si N down to 1.4 nm where the physical thickness is about 2.8 nm still shows charge trapping [9]. So, controlling the initial bulk trap density is the only way to reduce charge trapping.…”
Section: Discussionmentioning
confidence: 99%
“…Applying such a high gate voltage to our ultrathin dielectrics would lead to rapid device degradation under Fowler-Nordheim (FN) (rather than hot-carrier) stress. For example, the transconductance of a JVD transistor under 4.5 V stress would drop by 10% in about 2 s [8], while the same amount of degradation due to hot carrier stress under peak condition takes 5 10 s. (Extrapolated lifetime under 2-V FN stress is in excess of 10 s [8].) The hot-carrier stress was periodically interrupted, and transistor parameters such as saturation drain current , linear drain current , threshold voltage shift , peak transconductance , subthreshold swing , and gate leakage current were monitored.…”
Section: Device Fabrication and Characterizationmentioning
confidence: 99%
“…However, it is necessary to demonstrate good reliability of thin Si N before it can replace SiO as gate dielectric. Studies of time-dependent dielectric breakdown [5], [7] and time-dependent dielectric wearout [8] indicate that Si N under Fowler-Nordheim stress meets reliability requirements. It still remains to be shown that hot-carrier reliability of Si N gate dielectrics is acceptable.…”
Section: Introductionmentioning
confidence: 99%