Intrinsic and stress-induced traps in the direct tunneling current of 2.3-3.8 nm oxides and unified characterization methodologies of sub-3 nm oxides

Liu, C.T.; Ghetti, A.; Ma, Yutao; Alers, G. B.; Chang, Chao; Cheung, Kin P.; Colonell, Jennifer; Lai, Wei-Chih; Pai, C.S.; Liu, R.; Vaidya, H.; Clemens, J.T.

doi:10.1109/iedm.1997.649470

Cited by 19 publications

(8 citation statements)

References 4 publications

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“…This phenomena is very similar to the stress-induced leakage current (SILC) [13], where the increased leakage current is attributed to trap generation or local thinning in oxide [14]. In fact, Liu et al has also observed such excess leakage and attributed this effect as intrinsic traps [15]. However, our data suggests that such intrinsic traps are process-dependent and strongly related to the presence of native oxide.…”

Section: Methodssupporting

confidence: 81%

The effect of native oxide on thin gate oxide integrity

Chin

Lin

Chen³

et al. 1998

IEEE Electron Device Lett.

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We have studied the effect of native oxide on thin gate oxide integrity. Much improved leakage current of gate oxide can be obtained by in situ desorbing the native oxide using a HFvapor treated and H 2 backed process. Furthermore, extremely sharp interface between oxide and Si is obtained, and good oxide reliability is achieved even under a high current density stress of 11 A/cm 2 and a large charge injection of 7:9 2 10 4 C/cm 2 . The presence of native oxide will increase the interface roughness, gate oxide leakage current and stress-induced hole trap.

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Section: Methodssupporting

confidence: 81%

The effect of native oxide on thin gate oxide integrity

Chin

Lin

Chen³

et al. 1998

IEEE Electron Device Lett.

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“…Even though the applied voltage is gradually increasing after the occurrence of breakdown, the current increases but is obviously limited by carrier thermal generation. 10 It is noted that this current limitation of about 10 Ϫ2 A/cm 2 in Fig. 2 is not measurement protection limitation.…”

Section: Resultsmentioning

confidence: 96%

Breakdown characteristics of ultrathin gate oxides (<4 nm) in metal–oxide–semiconductor structure subjected to substrate injection

Huang

Hwu

2001

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Articles you may be interested inElectrical characteristics and reliability properties of metal-oxide-semiconductor field-effect transistors with Zr O 2 gate dielectric Lifetime-limited current in Cu-gate metal-oxide-semiconductor capacitors subjected to bias thermal stress J. Appl. Phys. 99, 034504 (2006); 10.1063/1.2168034 Temperature-induced voltage drop rearrangement and its effect on oxide breakdown in metal-oxidesemiconductor capacitor structure A diodelike conduction model for the postbreakdown current in metal-oxide-semiconductor structures J. Appl. Phys. 96, 6940 (2004); 10.1063/1.1812584Localization of gate oxide integrity defects in silicon metal-oxide-semiconductor structures with lock-in IR thermography Thin oxide property in a metal-oxide-semiconductor structure subjected to substrate injection from semiconductor into oxide is investigated by means of ramp-up and ramp-down current-voltage (I -V) measurements. Generally, gate injection causes catastrophic dielectric breakdown, and the damaged oxide suffers from permanent destruction which exhibits resistorlike behavior in the I -V curve. For substrate injection, however, there are three distinct modes existing in I -V characteristics. They are resistorlike, hysteresislike, and saturation, i.e., no breakdown. Their occurrence frequencies are dependent on the oxide thickness. For oxides thinner than 2.4 nm, in general, the gate current nearly saturates due to the limitation of minority carriers. For 3.9 nm oxide, the minority carrier generation rate increases due to trap generation near the Si surface. Thus the oxide sustains higher field and larger carrier injection causing destructive damage, i.e., resistorlike mode. For 3 nm oxide, sometimes a hysteresislike mode appears due to light damage in the oxide. The related characteristics of these three modes are studied and exhibit oxide thickness dependence. These phenomena are important to recent studies on devices with ultrathin gate oxides.

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“…It is observed that under positive bias the gate current decreases after stressing, and as the bias is larger than 0.75 V, the fresh and stressed curves are merged and are gradually saturated due to the limitation of minority-carrier generation. 22 To understand this phenomenon, we also investigate the I -V characteristics of an n-MOS capacitor with 1.8 nm oxide thickness. Figure 4 shows the fresh and stressed ͑Ϫ3 V͒ LVTC of an n-MOS capacitor under negative and positive bias conditions.…”

Section: Resultsmentioning

confidence: 99%

Anomalous low-voltage tunneling current characteristics of ultrathin gate oxide (∼2 nm) after high-field stress

Huang

Hwu

2001

Journal of Applied Physics

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The effect of oxide barrier shape change caused by stress-induced interface trap charges on the low-voltage tunneling current ͑LVTC͒ characteristics of ultrathin gate oxide ͑ϳ2 nm͒ is studied in this work. It was found that for an ultrathin gate oxide working in the direct tunneling regime, the LVTC behavior is strongly dependent on the barrier shape of the oxide. After high-field stress, anomalous LVTC phenomenon is observed. There is an invariant point existing in current-voltage curves. For a bias smaller than the value of the invariant point, the gate current decreases with stress time. However, for a bias larger than that, the gate current increases with stress time and then saturates. This phenomenon cannot be explained by conventional trap-assisted tunneling conduction, but by the change of tunneling probability due to barrier shape variation. An interface trap charge model is proposed to explain the observed invariant point mentioned above. From this, one can find the voltage corresponding to the midgap bias and, therefore, the initial effective oxide charge number density.

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Intrinsic and stress-induced traps in the direct tunneling current of 2.3-3.8 nm oxides and unified characterization methodologies of sub-3 nm oxides

Cited by 19 publications

References 4 publications

The effect of native oxide on thin gate oxide integrity

The effect of native oxide on thin gate oxide integrity

Breakdown characteristics of ultrathin gate oxides (<4 nm) in metal–oxide–semiconductor structure subjected to substrate injection

Anomalous low-voltage tunneling current characteristics of ultrathin gate oxide (∼2 nm) after high-field stress

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Intrinsic and stress-induced traps in the direct tunneling current of 2.3-3.8 nm oxides and unified characterization methodologies of sub-3 nm oxides

Cited by 19 publications

References 4 publications

The effect of native oxide on thin gate oxide integrity

The effect of native oxide on thin gate oxide integrity

Breakdown characteristics of ultrathin gate oxides (&lt;4 nm) in metal–oxide–semiconductor structure subjected to substrate injection

Anomalous low-voltage tunneling current characteristics of ultrathin gate oxide (∼2 nm) after high-field stress

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Breakdown characteristics of ultrathin gate oxides (<4 nm) in metal–oxide–semiconductor structure subjected to substrate injection