Internal Gettering in Bipolar Process: Effect on Circuit Performance and Relationship to Oxygen Precipitation Kinetics

Section: "-R Dmentioning

confidence: 99%

Effect of Postannealing on the Oxygen Precipitation and Internal Gettering Process in N/N+ (100) Epitaxial Wafers

Wijaranakula¹,

Matlock²,

Mollenkopf³

1988

“…The dislocation generation could be a serious problem in silicon wafers J a n u a r y 1 9 8 7 w i t h low m e c h a n i c a l s t r e n g t h s u c h as float zone silicon, w h i c h h a s n o o x y g e n to give d i s l o c a t i o n p i n n i n g (13,14), or i n t e r n a l l y g e t t e r e d wafers w i t h o u t o p t i m i z e d precipit a t e m o r p h o l o g y (15,16). A t h i g h t e m p e r a t u r e s t h e mec h a n i c a l S t r e n g t h of s i l i c o n is r e d u c e d (9), a n d t h e s e s t r e s s e s c a n g e n e r a t e d i s l o c a t i o n s a l o n g t h e n i t r i d e or p o l y p a t t e r n e d g e s (8,11,12).…”

Section: Resultsmentioning

confidence: 99%

“…It has been well established that stresses introduced during processing by thermal gradients during heating/ cooling (9, 10) or during poly (8) or nitride layer (11,12) depositions can generate dislocations. The dislocation generation could be a serious problem in silicon wafers w i t h low m e c h a n i c a l s t r e n g t h s u c h as float zone silicon, w h i c h h a s n o o x y g e n to give d i s l o c a t i o n p i n n i n g (13,14), or i n t e r n a l l y g e t t e r e d wafers w i t h o u t o p t i m i z e d precipit a t e m o r p h o l o g y (15,16) 17), a n d t h u s r e s u l t in h i g h dislocation densities at the pattern edges.…”

Section: Discussionmentioning

confidence: 99%

Effect of Pattern Orientation on the Resistance to Process‐Induced Dislocation Generation in (100) Silicon

Jastrzȩbski

Soydan

Armour

et al. 1987

Self Cite

The effect of orientation of patterns, made in poly and nitride layers deposited and defined over (100) silicon wafers, on dislocation generation during IC processing was investigated. By changing the pattern edges from the <110> to the <100> direction, the probability of dislocation generation was reduced. This can be explained by the orientation of stress raisers out of the {11 t} slip plane. As a result of defect reduction, the yields of CMOS and CCD circuits was improved.

“…This is consistent with experimental results described in other papers. 2,9 In addition, an increase in the leakage current can be seen in the voltage range from Ϫ2 to Ϫ6 V, compared with the leakage current of the reference oxide. The characteristics of the oxide immersed in the SPM solution are also shown in Fig.…”

Section: Methodsmentioning

confidence: 97%

Leakage Current Distribution and Dielectric Breakdown of Cu-Contaminated Thin SiO[sub 2]

Tokuda

Nishiguchi

Yamasaki

et al. 2004

Dielectric degradation of an intentionally Cu-contaminated SiO 2 film on a Si substrate was investigated using conducting atomic force microscopy and metal-oxide-semiconductor capacitors. Comparison of the results of both measurements clarified that local oxide leakage currents increased at random points except at the Cu particles. At the Cu particles, accelerated thermal oxidation leads to the formation of a thick SiO 2 layer at the interface with the Si substrate and suppression of the oxide leakage current. A combination of electrical evaluations and total reflection X-ray fluorescence analyses indicated that a high Cu concentration on a SiO 2 surface induced low-voltage dielectric breakdown, and a low Cu concentration inside the SiO 2 film induced high leakage current in a low electric field range.A continuous decrease in the gate oxide thickness of metaloxide-semiconductor ͑MOS͒ systems is inevitable in current ultralarge-scale integrated circuits ͑ULSIs͒. Ultrathin gate oxide with uniform thickness within a large-diameter wafer can be easily formed with either a low oxidation temperature or a short oxidation time. 1 However, it is difficult to establish an ultrathin gate oxide technology in the ULSI manufacturing process with high device yield and high reliability. 2,3 This is because both the yield and longterm reliability of the thin gate oxide are easily deteriorated by crystal originated particles 4 or bulk microdefects 5 in the Si wafer or by such phenomena as charge-up 6,7 and radiation 8 during ULSI manufacturing processes. In addition, one of the most problematic causes of reliability degradation in ULSI manufacturing is unintentional contamination such as by metal and organic matter. In particular, care should be taken to prevent contamination with metallic impurities with high diffusivity in all process steps. 2,3,9,10 The scaling of devices to submicrometer dimensions has constrained ULSI performance because of the RC (resistance ϫ capacitance) delay interconnection. The resistance of interconnection wiring can be lowered by choosing alternative conductor materials such as Cu, Ag, or other new materials. The purity of such materials is still low in comparison with those of other materials used in ULSIs. In adopting such materials, attention should be paid to not only the main elements but also the impurities. Cu with low resistivity and a cost advantage is profitable as a low-resistance interconnection material. However, the diffusivity of Cu is high in SiO 2 11 and Si. 12 For example, the diffusion length at 600°C for 60 min in Si is approximately 2 mm, 12 which is more than the Si wafer thickness. That is, even Cu atoms adsorbed at the back surface of the Si wafers during the manufacturing process may degrade the functions of ULSIs. In addition, the electronegativity of Cu is higher than that of Si. 13 Immersion in a diluted hydrofluoric acid ͑DHF͒ solution before the gate oxidation easily causes the adsorption of Cu on the bare Si surface. 14 In many of the previous studies, deterioration by t...