Interface synthesis for heterogeneous multi-core systems from transaction level models

ChoHansu,; AbdiSamar,; GajskiDaniel,

doi:10.1145/1273444.1254791

Cited by 5 publications

(3 citation statements)

References 4 publications

(3 reference statements)

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“…Cho et al [5] describe a tool for synthesizing a TLM into a universal RTL bridge that translates the canonical TLM interface into a target bus protocol using platform definitions and protocol libraries. The bridge contains a FIFO and a dedicated controller for each bus protocol.…”

Section: Related Workmentioning

confidence: 99%

Synthesis of optimized hardware transactors from abstract communication specifications

Lee

Park

Gerstlauer

2012

Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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Increasing system complexity and heterogeneity make system integration and communication synthesis a growing concern. Even with transaction-level modeling and high-level synthesis of hardware, communication interfaces still have to be manually designed at a low protocol level. To address this challenge, we present a design flow for automatic synthesis of hardware transactors, which realize abstractly specified communication semantics on top of protocol-level transactions. Transactor synthesis is tightly coupled with high-level synthesis of computation for integrated computation/communication co-design of complete hardware processors, thus establishing a seamless path from abstract system specifications down to hardware implementations in synthesizable RTL. The flow supports a generic set of communication semantics and target implementations, where transactors are custom-generated for a specific application and architecture combination. Furthermore, we develop protocol stack optimizations that reduce the area and performance overhead of synthesized communication interfaces. We have applied our synthesis flow to several industrial-strength examples under various communication settings. Results show that synthesized interfaces are comparable to manual designs in terms of area and latency, where protocol stack optimizations can reduce area and latency overhead by up to 77% and 21%, respectively.

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Section: Related Workmentioning

confidence: 99%

Synthesis of optimized hardware transactors from abstract communication specifications

Lee

Park

Gerstlauer

2012

Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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“…SystemC provides a better integration with the existing SoC design, simulation and verification context. To enhance the design abstraction level, ESL (Electronic System design Language) is employed in [5] for interface synthesis. A universal bridge of two busses can be characterized subject to the transaction level modeling of IP and a protocol library.…”

Section: Introduction and Previous Workmentioning

confidence: 99%

An IP interface design compiler with SystemC based input specifications

Hwang

Chen

2014

2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)

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We present an interface synthesis tool (design compiler) which can generate interface circuits automatically to expedite the IP (silicon intellectual property) integration process in SoC designs. The protocol specification issue is first addressed and a programming paradigm in SystemC language is developed. The methodology for interface synthesis is next elaborated. Conventional compiler techniques such as lexical analysis, syntax parsing and code generation are applied plus the new processing specific to interface synthesis. This includes protocol signal mapping proxy for additional semantic information, interface FSM synthesis for the controller of protocol conversion and architecture template mapping for the underlined hardware. Various interface design examples are conducted and the experimental results show the competitiveness of the proposed synthesis tool.

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“…Optimization in latency and data bandwidth was also addressed. In [6], automatic interface synthesis for heterogeneous MPSoC was addressed. The system was described using transaction level models (TLM).…”

Section: Introductionmentioning

confidence: 99%

Automatic IP Interface Synthesis Supporting Multi-layer Communication Protocols in SoC Designs

Hwang

Luo

2009

2009 Fifth International Conference on Information Assurance and Security

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We present an automatic interface synthesis system to expedite the IP (silicon intellectual property) integration process in SoC designs.The concept of multi-layer communication protocols is incorporated into the synthesis process so that interface design targeting different levels of functionality and circuit complexity can be generated automatically. The multi-layered interface architecture template designs are addressed in the first place. We then outline the methodology of interface synthesis, which includes protocol specifications, signal mapping & timing adjustment, interface FSM, and architecture mapping. Interface designs for several benchmark systems are developed using different synthesis options. Besides the advantage of greatly shortened design cycle, the experimental results do show the competitiveness of the automatically generated designs against the manual designs.

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Interface synthesis for heterogeneous multi-core systems from transaction level models

Cited by 5 publications

References 4 publications

Synthesis of optimized hardware transactors from abstract communication specifications

Synthesis of optimized hardware transactors from abstract communication specifications

An IP interface design compiler with SystemC based input specifications

Automatic IP Interface Synthesis Supporting Multi-layer Communication Protocols in SoC Designs

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