Interface characterization of atomic layer deposited high-k on non-polar GaN

Abstract

The interface properties between dielectrics and semiconductors are crucial for electronic devices. In this work, we report the electrical characterization of the interface properties between atomic layer deposited Al2O3 and HfO2 on non-polar a-plane (112¯0) and m-plane (11¯00) GaN grown by hybrid vapor phase epitaxy. A metal oxide semiconductor capacitor (MOSCAP) structure was used to evaluate the interface properties. The impact of annealing on the interface properties was also investigated. The border trap in the oxide, characterized by the capacitance-voltage (C-V) hysteresis loop, was low. The interface state density (Dit), extracted using the ac conductance method, is in the range of 0.5 × 1012/cm2 eV to 7.5 × 1011/cm2 eV within an energy range from 0.2 eV to 0.5 eV below the conduction band minimum. The m-plane GaN MOSCAPs exhibited better interface properties than the a-plane GaN MOSCAPs after annealing. Without annealing, Al2O3 dielectrics had higher border trap density and interface state density compared to HfO2 dielectrics. However, the annealing had different impacts on Al2O3 dielectrics as compared to HfO2. Our results showed that the annealing degraded the quality of the interface in HfO2, but it improved the quality of the interface in Al2O3 devices. The annealing also reduced the positive trapped oxide charge, resulting in a shift of C-V curves towards the positive bias region.

On the Conduction Properties of Vertical GaN n-Channel Trench MISFETs

“…Comparable interface trap density values are calculated for the devices on the examined substrates in the range of 5 to 11 × 10 12 eV -1 cm -2 . These values are slightly larger than reported values for lateral MIS capacitors on non-polar GaN [33]. One reason that may explain the larger interface trap density is that unlike epitaxial non-polar lateral structures, in the vertical MISFET devices the non-polar faces are damaged by the dry etch process.…”

Interfacial and electrical properties of nanolaminated HfO2/Al2O3 dielectrics on GaN with an AlN interlayer

“…It was shown in the gallium oxide (GaO x )/GaN MOS capacitor that the GaO x annealed in ambient N 2 or without post deposition annealing did not exhibit any reasonable C-V characteristics and was attributed to the oxygen content in the GaO x layer [26]. Furthermore, Jie et al did not obtain the exact accumulation capacitance in the Al 2 O 3 /m-plane GaN MOS capacitor because of the high leakage current in the accumulation region [27]. The presence of a disordered or defective interfacial layer caused the frequency dispersion in the accumulation might also increase the leakage current for the single bilayer.…”

A Simulation Study on the Effects of Interface Charges and Geometry on Vertical GAA GaN Nanowire MOSFET for Low-Power Application

“…2, three trap Models I, II, and III are considered in this work. The trap models are based on the trap information for the Al 2 O 3 /GaN interface with a distributed trap density (D IT ) and trap energy (E IT ) from 0.0 -0.5 eV, given in [28], [29]. Non-polar sidewall of a Wurtzite GaN-based nanowire can be an m-plane or a-plane or a mixture of both.…”