A Simulation Study on the Effects of Interface Charges and Geometry on Vertical GAA GaN Nanowire MOSFET for Low-Power Application

Abstract

The effects of interface charges on the performances of gate-all-around (GAA) GaN vertical nanowire MOSFETs with different geometries have been studied. Geometrical effect on the gate current of vertical GAA GaN nanowire MOSFET has also been analysed for the first time. In the ideal condition, the circular geometry nanowire (CGN) MOSFET exhibits the best performance with subthreshold swing (SS) of 62 mV/dec, drain-induced barrier lowering (DIBL) of 14 mV/V, and ON/OFF current ratio (I ON /I OFF ) of ∼10 8 . The triangular or hexagonal geometry nanowire (TGN or HGN) MOSFET suffer from large gate leakage current due to the field enhancement at sidewall corners. It is also known that interface traps at the sidewall surface of vertical nanowires deteriorate the overall device performance. The HGN MOSFET with m-plane sidewall demonstrates the best performance with SS of 69 mV/dec and DIBL of 13 mV/V, while the TGN MOSFET with a-plane sidewall exhibits the worst performance with SS of 112 mV/dec and DIBL of 101 mV/V.

A proposal and simulation analysis for a novel architecture of gate-all-around polycrystalline silicon nanowire field effect transistor

“…This allows the acceptor traps to ionize sufficiently and increases the free electron concentration. Previous studies [19]- [21] have shown that triangular nanowires also have an increase in the free electron concentration. The corner effect is primarily responsible for the high performance of device, which is relatively higher than the performance reported in the literature [16], as shown in Table 3.…”

“…According to the realization process of gate-allaround poly-SiNW FETs reported in the literature, the sections of these SiNWs have a quasi-circular shape or square shape with rounded edges. Previous work [19]- [21] showed that the shape of SiNW significantly affects the device's performance. Particularly when the SiNW shape is triangular, where the free electron concentration increases near the corners.…”

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

“…Ni silicides have been widely used; moreover, the relaxation of the SiGe layer could be diminished by introducing carbon in the SiGe layers [176][177][178][179]. The SEG process of SiGe suffers from a pattern-dependency problem when, in the profile of the epi-layer, the exposed Si areas in openings (for example, in the S/D regions) in a chip differ for different layouts [19][20][21]38,[180][181][182][183]. The main reason behind this problem is the non-uniform consumption of reactant gases (GeH 4 , SiH 4 , DCS, HCl) over a patterned wafer (global effect) or an array of openings inside a chip (local effect), when the layout of chip is changed.…”

“…Figure 5 shows the ferroelectric VSAFETs (Fe-VSAFETs) with a self-a metal gate [13]. Fe-VSAFETs have excellent electrical characteristics such as ION/IOF of more than 10 7 , leakage currents of less than 1pA, long retention times, program times of around 100 ns, and the largest memory window (MW) at about 2.3 V. Further studies on GAAFET have been reported, including high-mobility c materials, e.g., Ge/GeSn [14][15][16][17] and III-V [18], and wide bandgap materials, e.g [19,20]. Further studies on GAAFET have been reported, including high-mobility channel materials, e.g., Ge/GeSn [14][15][16][17] and III-V [18], and wide bandgap materials, e.g., GaN [19,20].…”