Interconnection Media

Giffels, Carl A.; Gashler, R. J.; Morabito, J.M.; Striny, Kurt M.

doi:10.1002/j.1538-7305.1987.tb00216.x

Cited by 5 publications

(1 citation statement)

References 4 publications

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“…In this process, solder is applied to the contact pads of chip and substrate wafers byevaporation through a metal mask before reflow assembly. [1][2][3][4] For gated-diode cross-point (GDX) devices in 5ESS® switching systems, spherical solder preforms are attached directly to the metallized pads ofleadless chip carriers. These solder-bumped chip carriers are then surface-mounted on ceramic substratesof hybridintegrated-circuit modules.…”

Section: Introductionmentioning

confidence: 99%

Automated Visual Inspection of Solder Bumps

Ray

1988

At&T Technical Journal

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This paper describes a computer vision technique for automated inspection of solder bumps on leadless chip carriers and metallized wafers for advanced VLSI (very‐large‐scale integration) packaging. It is based on high‐contrast imaging of soldered surfaces against a reflective background using dark‐field illumination for selective enhancement of surface topography. A brightfield image is also used for resolving ambiguities in image understanding. Gray‐scale images are analyzed using vision algorithms to detect topographic discontinuities of soldered surfaces and to identify solder‐bump defects.

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Section: Introductionmentioning

confidence: 99%

Automated Visual Inspection of Solder Bumps

Ray

1988

At&T Technical Journal

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Interconnection System Requirements and Modeling

Pinnel

Knausenberger

1987

At&T Technical Journal

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M. Robert Pinnel is head of the Systems Analysis and Technology Planning Department at AT&T Bell Laboratories in Whippany. New Jersey. and Wulf H. Knausenbergeris a supervisor in that department. Mr: Pinnel is responsible for trend analysis, long-range planning, and development of advanced applications for interconnection technology and hardware. He joined the company in 1970 and has a B.S. in electrical engineering, an M.S. in metallurgy. and a Ph.D. in materials engineering, all from Drexel University Mr: Knausenberger is responsible for interconnection system analysis and project planning. He joined the company in 1970 and has a B.S. in engineering science and a Ph.D. in solidstate science, both from Pennsylvania State UniversityRapid technological advances in electronic systems technologies are placing increasingly severe demands on interconnection media. One primary driving force is the evolutionary advance in the scale of integration in silicon with its inherent cost and performance advantages. Another is the revolutionary development of photonics, which is rapidly integrating into most levels of the interconnection hierarchy. Increasingly, the interconnection environment dominates and limits the performance of large-scale electronic systems. This paper explores traditional levels of interconnection from Ie chip packages to frames. It shows how the interconnection levels interrelate and must be improved simultaneously to achieve full performance and cost benefits. The first major step in this evolution is well underway with the rapid transition to surface mounting of devices. We describe advanced modeling tools and relate the results of modeling analysis to the challenges faced by interconnection technology hardware and materials. PerspectiveDriven byrapid evolutionary and revolutionary technological advances, the electronics industry is enteringa period ofsignificant growth and change. Formany years, the dual in-line package (DIP) served the needsforpackaging silicon chips. Conventional printed-wiring substrates, connectors, andbackplanes have successfully interconnected the various silicon and othercomponents that dothe systemfunctions.However, many believe that the DIP has run out of steam' and new integrated circuit (IC) packaging technologies are required. This has implications on each succeeding level of interconnection up to the full-system level, and a large-scale electronic system's performance 45

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Report: Computer-Aided Engineering and Design for Interconnection Technology

Rosenthal

Dishman

1987

At&T Technical Journal

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Interconnection Media

Cited by 5 publications

References 4 publications

Automated Visual Inspection of Solder Bumps

Automated Visual Inspection of Solder Bumps

Interconnection System Requirements and Modeling

Report: Computer-Aided Engineering and Design for Interconnection Technology

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