Interconnection System Requirements and Modeling

Abstract

M. Robert Pinnel is head of the Systems Analysis and Technology Planning Department at AT&T Bell Laboratories in Whippany. New Jersey. and Wulf H. Knausenbergeris a supervisor in that department. Mr: Pinnel is responsible for trend analysis, long-range planning, and development of advanced applications for interconnection technology and hardware. He joined the company in 1970 and has a B.S. in electrical engineering, an M.S. in metallurgy. and a Ph.D. in materials engineering, all from Drexel University Mr: Knausenberger is responsible for interconnection system analysis and project planning. He joined the company in 1970 and has a B.S. in engineering science and a Ph.D. in solidstate science, both from Pennsylvania State UniversityRapid technological advances in electronic systems technologies are placing increasingly severe demands on interconnection media. One primary driving force is the evolutionary advance in the scale of integration in silicon with its inherent cost and performance advantages. Another is the revolutionary development of photonics, which is rapidly integrating into most levels of the interconnection hierarchy. Increasingly, the interconnection environment dominates and limits the performance of large-scale electronic systems. This paper explores traditional levels of interconnection from Ie chip packages to frames. It shows how the interconnection levels interrelate and must be improved simultaneously to achieve full performance and cost benefits. The first major step in this evolution is well underway with the rapid transition to surface mounting of devices. We describe advanced modeling tools and relate the results of modeling analysis to the challenges faced by interconnection technology hardware and materials. PerspectiveDriven byrapid evolutionary and revolutionary technological advances, the electronics industry is enteringa period ofsignificant growth and change. Formany years, the dual in-line package (DIP) served the needsforpackaging silicon chips. Conventional printed-wiring substrates, connectors, andbackplanes have successfully interconnected the various silicon and othercomponents that dothe systemfunctions.However, many believe that the DIP has run out of steam' and new integrated circuit (IC) packaging technologies are required. This has implications on each succeeding level of interconnection up to the full-system level, and a large-scale electronic system's performance 45

Chip-to-board interconnects for high-performance computing

“…The interconnect hierarchy [4] was conceived in the 1960s as a means to describe the connections to be made between the different levels of integration in the system. It allowed to distinguish the requirements on different interconnects Levels.…”

“…The interconnect hierarchy [4,5] logically partitions a system into various levels that are interconnected by physical connections. The model had been created and is used for electrical connections, but may well be applied to understand the system partitioning in the optical domain as well.…”