Interconnect tuning strategies for high-performance ICs

Abstract

Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses, widths and spacings in multi-layer interconnect to simultaneously optimize signal distribution, signal performance, signal integrity, and interconnect manufacturability and reliability. This is a key activity in most leading-edge design projects, but has received little attention in the literature. Our work provides the first technology-specific studies of interconnect tuning in the literature. We center on global wiring layers and interconnect tuning issues related to bus routing, repeater insertion, and choice of shielding/spacing rules for signal integrity and performance. We address four basic questions. (1) How should width and spacing be allocated to maximize performance for a given line pitch? (2) For a given line pitch, what criteria affect the optimal interval at which repeaters should be inserted into global interconnects? (3) Under what circumstances are shield wires the optimum technique for improving interconnect performance? (4) In global interconnect with repeaters, what other interconnect tuning is possible? Our study of question (4) demonstrates a new approach of offsetting repeater placements that can reduce worstcase cross-chip delays by over 30% in current technologies.

Minimising Dynamic Power Consumption in On-Chip Networks

“…Delay and energy values were then obtained by running HSPICE on a distributed RC model of the interconnect -including all coupling capacitances. Results are summarised in Table I for both in-line and staggered repeater placements [4]. Energy is reported as the energy per transition, per mm, averaged over 500 random input vectors.…”

Manufacturing-aware physical design

“…The addition of dummy fill increases coupling capacitance [13] and, as buffer distances between dummy and actual features decrease, reduces the benefits of spacing wires apart. A second observation is that repeater staggering [1,14] provides an elegant and simple approach to reduce crosstalk. The technique gives good control of delay uncertainty and limits the maximum amount of worst-case coupling (essentially, compensating with best-case coupling), but incurs high costs in terms of layout perturbation, via blockage, and power.…”

“…Switch factors depend on the aggressor 1 Though via resistance is not explicitly mentioned in the equation, we add via resistance to the resistance of the interconnect segment which is next to the via. Table 2: Comparison of results of our approach versus HSpice for a three-line coupled system.…”

Interconnect parasitic extraction in the digital IC design methodology

“…Break long interconnect spans by inserting buffers [39]. This reduces the quadratic effect of RC interconnect delays.…”