Interconnect parasitic extraction in the digital IC design methodology

Kamon, M.; McCormick, S.; Shepard, K.

doi:10.1109/iccad.1999.810653

Cited by 14 publications

(7 citation statements)

References 45 publications

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“…Naturally, process variations and layout imbalances affect any equalization countermeasures. Furthermore, layout and RC-extraction through the post-layout analysis improve the accuracy of simulations [36,37]. Ignoring such post-layout and post-production can mitigate the leakages.…”

Section: Analysis Resultsmentioning

confidence: 99%

Balancing the Leakage Currents in Nanometer CMOS Logic—A Challenging Goal

2021

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The imbalance of the currents leaked by CMOS standard cells when different logic values are applied to their inputs can be exploited as a side channel to recover the secrets of cryptographic implementations. Traditional side-channel countermeasures, primarily designed to thwart the dynamic leakage behavior, were shown to be much less powerful against this static threat. Thus, a special protection mechanism called Balanced Static Power Logic (BSPL) has been proposed very recently. Essentially, fundamental standard cells are re-designed to balance their drain-source leakage current independent of the given input. In this work, we analyze the BSPL concept in more detail and reveal several design issues that limit its effectiveness as a universal logic library. Although balancing drain-source currents remains a valid approach even in more advanced technology generations, we show that it is conceptually insufficient to achieve a fully data-independent leakage behavior in smaller geometries. Instead, we suggest an alternative approach, so-called improved BSPL (iBSPL). To evaluate the proposed method, we use information theoretic analysis. As an attack strategy, we have chosen Moments-Correlating DPA (MCDPA), since this analysis technique does not depend on a particular leakage model and allows a fair comparison. Through these evaluation methods, we show iBSPL demands fewer resources and delivers better balance in the ideal case as well as in the presence of process variations.

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Section: Analysis Resultsmentioning

confidence: 99%

Balancing the Leakage Currents in Nanometer CMOS Logic—A Challenging Goal

2021

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“…Subsequent developments using iterative methods resulted in methods like PVL that overcome many of the deficiencies of the earlier AWE efforts, and stability is now guaranteed using techniques like Arnoldi transformations [39]. The interconnect delay problem has become so important that it is now driving the layout generation to get in-time timing closure, and that it even is becoming essential for synthesis (where, of course, estimation techniques must be used) [40].…”

Section: A Numerical Simulation Of Analog and Mixed-signal Circuitsmentioning

confidence: 99%

Computer-aided design of analog and mixed-signal integrated circuits

2000

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“…The more the operation frequency is, the more impact on the system of parasitic capacitance and induction. This is true for radio frequency communication devices, as well as very large-scale integration circuits and multilayer printed-circuit boards [1,2].…”

Section: Introductionmentioning

confidence: 99%

Monte Carlo Algorithms for the Extracting of Electrical Capacitance

Кузнецов¹,

Сипин²

2021

Mathematics

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We present new Monte Carlo algorithms for extracting mutual capacitances for a system of conductors embedded in inhomogeneous isotropic dielectrics. We represent capacitances as functionals of the solution of the external Dirichlet problem for the Laplace equation. Unbiased and low-biased estimators for the capacitances are constructed on the trajectories of the Random Walk on Spheres or the Random Walk on Hemispheres. The calculation results show that the accuracy of these new algorithms does not exceed the statistical error of estimators, which is easily determined in the course of calculations. The algorithms are based on mean value formulas for harmonic functions in different domains and do not involve a transition to a difference problem. Hence, they do not need a lot of storage space.

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Interconnect parasitic extraction in the digital IC design methodology

Abstract: Abstract

Cited by 14 publications

References 45 publications

Balancing the Leakage Currents in Nanometer CMOS Logic—A Challenging Goal

Balancing the Leakage Currents in Nanometer CMOS Logic—A Challenging Goal

Computer-aided design of analog and mixed-signal integrated circuits

Monte Carlo Algorithms for the Extracting of Electrical Capacitance

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