Interconnect-aware device targeting from PPA perspective

Badaroglu, Mustafa; Xu, Jeff

doi:10.1145/2966986.2980068

Cited by 4 publications

(3 citation statements)

References 3 publications

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“…The results demonstrate that our next generation process has achieved an average performance improvement of 57% over the previous generation, far exceeding the 30% predicted by reference [5,24]. Based on this average increase in frequency (57%), we plotted an expected frequency curve as shown by the dashed line in Fig.…”

Section: Timing Results Analysismentioning

confidence: 77%

“…[20]. The development of IC products dictated the need for More Moore scaling to bring the PPA value for node-to-node scaling (every 2-3 years) [5,24]:…”

Section: Technology Scalingmentioning

confidence: 99%

“…In the post-Moore era, integrated circuit science and technology will evolve in three directions: "More Moore", "More than Moore", and "Beyond CMOS" [1,2]. Regardless of the pursued direction, evaluating the performance of integrated circuit (IC) processes is becoming increasingly crucial yet challenging [3,4,5]. Firstly, with regards to "More Moore", as CMOS technology approaches its physical and engineering limits, process performance deviates from expectations due to process variations [6,7], and increased devicerelated physical effects make process performance evaluation highly intricate.…”

Section: Introductionmentioning

confidence: 99%

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Power, performance, and area evaluation across 180nm-28nm technology nodes based on benchmark circuits

Yin,

Li,

Zhang

et al. 2024

IEICE Electron. Express

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In this study, we proposed a method that could efficiently and comprehensively evaluate power-performance-area (PPA) characteristics of CMOS processes across multiple technology nodes. According to the International Semiconductors Technology Roadmaps (ITRS), we have designed and implemented a series of benchmark Ring Oscillator (RO) circuits using a full-scale downsizing approach from 180nm half-pitch node to 28nm node. Simultaneously, we conducted simulations, analysis, and layout design for RO circuits based on six low-leakage (LL) processes: 180nm, 130nm, 90nm, 65nm, 40nm, and 28nm processes. Through longitudinal analysis and comparison of the PPA characteristics across these six processes, the process quality can be better understood, and some reliable conclusions can be drawn to guide design metrics. The proposed method and benchmark circuits can be well extended to future advanced technology nodes.

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Section: Timing Results Analysismentioning

confidence: 77%

“…[20]. The development of IC products dictated the need for More Moore scaling to bring the PPA value for node-to-node scaling (every 2-3 years) [5,24]:…”

Section: Technology Scalingmentioning

confidence: 99%