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Badaroglu, Mustafa

doi:10.1109/irds54852.2021.00010

Cited by 24 publications

(30 citation statements)

References 35 publications

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“…Recent studies show tremendous advances in the achievement of the ideal Mott–Schottky contact and the lowering of the contact resistance in 2D FETs [ 7 , 8 , 9 ]. The value of the contact resistance in 2D-materials-based transistors is approaching the requirement of the International Roadmap for Devices and Systems (IRDS) 2024 targets of logic transistors [ 10 ]. It is believed that a summary of emerging strategies to realize contact engineering in 2D FETs is urgently needed.…”

Section: Introductionmentioning

confidence: 99%

Recent Progress in Contact Engineering of Field-Effect Transistor Based on Two-Dimensional Materials

et al. 2022

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Two-dimensional (2D) semiconductors have been considered as promising candidates to fabricate ultimately scaled field-effect transistors (FETs), due to the atomically thin thickness and high carrier mobility. However, the performance of FETs based on 2D semiconductors has been limited by extrinsic factors, including high contact resistance, strong interfacial scattering, and unintentional doping. Among these challenges, contact resistance is a dominant issue, and important progress has been made in recent years. In this review, the Schottky–Mott model is introduced to show the ideal Schottky barrier, and we further discuss the contribution of the Fermi-level pinning effect to the high contact resistance in 2D semiconductor devices. In 2D FETs, Fermi-level pinning is attributed to the high-energy metal deposition process, which would damage the lattice of atomically thin 2D semiconductors and induce the pinning of the metal Fermi level. Then, two contact structures and the strategies to fabricate low-contact-resistance short-channel 2D FETs are introduced. Finally, our review provides practical guidelines for the realization of high-performance 2D-semiconductors-based FETs with low contact resistance and discusses the outlook of this field.

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Section: Introductionmentioning

confidence: 99%

Recent Progress in Contact Engineering of Field-Effect Transistor Based on Two-Dimensional Materials

et al. 2022

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“…Such investigation has not been given due attention in charge plasma based junctionless TFET devices. In RF communication systems, modeling the parasitic capacitances in the power area scaling has become very crucial as reported in the 2017 edition of IRDS 35 . As shown in Equations (4) and (5), 25 there is a direct reliance of parasitic capacitances on these Y parameters and frequency.…”

Section: Resultsmentioning

confidence: 99%

“…In RF communication systems, modeling the parasitic capacitances in the power area scaling has become very crucial as reported in the 2017 edition of IRDS. 35 As shown in Equations ( 4) and ( 5), 25 there is a direct reliance of parasitic capacitances on these Y parameters and frequency. Y 11 , Y 22 , Y , and Y 21 are the short circuit input admittance, output admittance, forward transfer admittance, and reverse transfer admittance, respectively.…”

Section: Comparative Analog/rf Performance Analysismentioning

confidence: 99%

Impact of tunnel gate process variations on analog/radio frequency (microwave) and small signal parameters of hetero‐material tunneling interfaced charge plasma junctionless tunnel field effect transistor

Sharma

Chaujar

2022

Circuit Theory & Apps

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This paper proposes a dual metal gate, hetero-material tunneling interfaced junctionless tunnel field effect transistor (TFET), (DMG-HJLTFET), utilizing III-V compound semiconducting materials, InAs (low band-gap source material)/GaAs (higher band-gap channel and drain material) by applying the band-gap and dual material gate engineering. The 2-D TCAD simulations have been executed to explore the impact of tunnel gate process variations-work function and length on DC and analog figure of merits (FOMs) of DMG-HJLTFET. The extracted result parameters have also been compared to SMG (single metal gate)-HJLTFET and conventional Si-JLTFET. The DMG-HJLTFET attains improved ON current in the range of 88.5 Â 10 À6 A/μm and OFF current remains as low as 2.89 Â 10 À16 A/μm. It exhibits a high current switching ratio of 3.1 Â 10 11 as compared to SMG-HJLTFET (I ON = 24 Â 10 À6 A/μm and I ON /I OFF = 1.4 Â 10 11 ) and Si-JLTFET (I ON = 7 Â 10 À6 A/μm and I ON /I OFF = 1.8 Â 10 6 ). Further, the radio frequency/microwave (RF) parameters such as power gains (h 12 , UPG, and Gma), f max , and GBP have been compared for all three aforementioned devices. Moreover, the small signal admittance (Y) parameters have been examined to explore the possible scope of DMG-HJLTFET for future internet of everything communications and fast switching applications.

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“…The gate lengths of metal-oxide-semiconductor field-effect transistors have been successfully reduced to below 5 nm to meet the needs of big data, cloud computing, mobile devices, self-driving electric vehicles, and artificial intelligence applications (i.e., the Fourth Industrial Revolution). − Short-channel effects such as punch-through, gate-leakage current ( I g ), channel-length modulation, drain-induced barrier reduction, and threshold voltage ( V th ) roll-off must be eliminated to further reduce the scale of transistor features during the pursuit of improvements in power, performance, area, and cost metrics. , High- k gate dielectrics can resolve I g problems, and the silicon-on-insulator technology eliminates the punch-through effects that result from the substrate-leakage current. Furthermore, short-channel effects are less significant in three-dimensional structures such as fin, multi-gate, gate-all-around, and nanosheet field-effect transistors, where the gate control is substantially improved.…”

Section: Introductionmentioning

confidence: 99%

Junctionless Electric-Double-Layer MoS₂ Field-Effect Transistor with a Sub-5 nm Thick Electrostatically Highly Doped Channel

Jeon

Park

et al. 2023

ACS Appl. Mater. Interfaces

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Junctionless transistors are suitable for sub-3 nm applications because of their extremely simple structure and high electrical performance, which compensate for short-channel effects. Two-dimensional semiconductor transition-metal dichalcogenide materials, such as MoS2, may also resolve technical and fundamental issues for Si-based technology. Here, we present the first junctionless electric-double-layer field-effect transistor with an electrostatically highly doped 5 nm thick MoS2 channel. A double-gated MoS2 transistor with an ionic-liquid top gate and a conventional bottom gate demonstrated good transfer characteristics with a 104 on–off current ratio, a 70 mV dec–1 subthreshold swing at a 0 V bottom-gate bias, and drain-current versus top-gate-voltage characteristics were shifted left significantly with increasing bottom-gate bias due to an electrostatically increased overall charge carrier concentration in the MoS2 channel. When a bottom-gate bias of 80 V was applied, a shoulder and two clear peak features were identified in the transconductance and its derivative, respectively; this outcome is typical of Si-based junctionless transistors. Furthermore, the decrease in electron mobility induced by a transverse electric field was reduced with increasing bottom-gate bias. Numerical simulations and analytical models were used to support these findings, which clarify the operation of junctionless MoS2 transistors with an electrostatically highly doped channel.

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More Moore

Cited by 24 publications

References 35 publications

Recent Progress in Contact Engineering of Field-Effect Transistor Based on Two-Dimensional Materials

Recent Progress in Contact Engineering of Field-Effect Transistor Based on Two-Dimensional Materials

Impact of tunnel gate process variations on analog/radio frequency (microwave) and small signal parameters of hetero‐material tunneling interfaced charge plasma junctionless tunnel field effect transistor

Junctionless Electric-Double-Layer MoS₂ Field-Effect Transistor with a Sub-5 nm Thick Electrostatically Highly Doped Channel

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More Moore

Cited by 24 publications

References 35 publications

Recent Progress in Contact Engineering of Field-Effect Transistor Based on Two-Dimensional Materials

Recent Progress in Contact Engineering of Field-Effect Transistor Based on Two-Dimensional Materials

Impact of tunnel gate process variations on analog/radio frequency (microwave) and small signal parameters of hetero‐material tunneling interfaced charge plasma junctionless tunnel field effect transistor

Junctionless Electric-Double-Layer MoS2 Field-Effect Transistor with a Sub-5 nm Thick Electrostatically Highly Doped Channel

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Product

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Junctionless Electric-Double-Layer MoS₂ Field-Effect Transistor with a Sub-5 nm Thick Electrostatically Highly Doped Channel