Integration of large-scale FPGA and DRAM in a package using chip-on-chip technology

Wang, Michael X.; Suzuki, K.; Dai, Wayne Wei-Ming; Low, Y.L.; O'Conner, K.J.; Tai, K.L.

doi:10.1145/368434.368606

Cited by 5 publications

(5 citation statements)

References 9 publications

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“…To the best of my knowledge, this was the first time that the term "System in Package" was used in a conference and in publications. In four companion papers with King Tai, a former AT&T fellow, we proposed the term "System in Package (SiP)" as the generalization of System on Chip (SoC) [9,12,5,4]. The term SiP was not popular 15 years ago but is now widely used in the industry, mainly due to a need for miniaturization of handheld devices such as smartphones and smart wearable devices, as well as a need for logic and DRAM integration and digital and RF integration, which sometimes cannot be cost effectively or performance efficiently integrated into an SoC.…”

Section: "Moore Stretch"mentioning

confidence: 99%

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Historical Perspective of System in Package (SiP)

Dai¹

2016

IEEE Circuits Syst. Mag.

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Section: "Moore Stretch"mentioning

confidence: 99%

“…At the same special session at ASP-DAC 2000, my former Ph.D. students and I, together with King Tai and AT&T researchers, presented a field programmable SiP containing one ORCA 3T/125 FPGA and 4 MByte DRAM [12] (Fig. 19).…”

Section: Dram and Fpga Integration And Area I/o Drammentioning

confidence: 99%

Historical Perspective of System in Package (SiP)

Dai¹

2016

IEEE Circuits Syst. Mag.

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“…Technological research in microelectronics is geared toward reducing component shape and sizes for better miniaturization of assemblies. 1 Among the main technologies developed for this purpose, Chip-on-Chip (CoC) assemblies, [2][3][4] mount two chips with different functions (e.g., power and control) in a sandwich. Crucially, this technology employs polymers, which are both physically and chemically resistant even at high operating temperatures, while also having low dielectric constants (to guarantee electrical insu-lation), high breakdown voltage resistance, and dimensional stability.…”

Section: Introductionmentioning

confidence: 99%

Polyethersulfone‐epoxy terminated materials as thermosetting resins for microelectronic devices

Scamporrino¹,

Mineo²,

Scamporrino³

et al. 2009

J. Polym. Sci. A Polym. Chem.

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A totally aromatic polyether/sulfone resin (PES‐E) was synthesized and tested as an insulating glue in the construction of a Chip‐on‐Chip (CoC) device. PES‐E, essentially constituted of open‐chain macromolecules of low molecular mass (Mn of about 3000 Da) with hydroxy and/or epoxy end‐groups, has a glass transition temperature of about 150 °C and is subject to crosslinking at temperatures higher than 320 °C. A CoC device was assembled using a five‐step process by interposing a layer of PES‐E between two chips. After curing, SEM cross section images showed a homogeneous crosslinked resin layer well stuck (flick and shear tests) to both chips. The chemical structure of the chains and the hydroxy/epoxy end‐groups ratio were optimized to obtain a crosslinked material with good adhesion and sufficient flexibility to avoid cracking during assembly and use. © 2009 Wiley Periodicals, Inc. J Polym Sci Part A: Polym Chem 47: 5682–5689, 2009

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“…One of them is our F P G N D M Sip module, which integrates large-scale FPGA and multi-bank DRAM in a package to provide high bandwidth memory access [4]. This is the first SIP module integrating FPGA and DRAM using chip-on-chip (CoC) technology.…”

Section: Introductionmentioning

confidence: 99%

Memory and logic integration for System-in-a-Package

Wang

Suzuki²,

Sakai³

et al.

ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

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System-in-a-Package (Sip), a generalization of System-an-a-Chip (SoC). provides a cost-efective solution for largescale mernoPy and logic integration and an attractive alternative f o r enibedded memovy. The key elements of Sip memory/logic integration technology include IO redistribution; solder btimping; and flip chip assembly. Two Sip plaflorms: Chip-on-Chip technology and ChipLaminate-Chip technology are introduced in this paper. An innovative conjgurable area-IO memory architecture for System-in-a-Package is presented. A 512K SRAMchip has been designed io ver& this approach.

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Integration of large-scale FPGA and DRAM in a package using chip-on-chip technology

Cited by 5 publications

References 9 publications

Historical Perspective of System in Package (SiP)

Historical Perspective of System in Package (SiP)

Polyethersulfone‐epoxy terminated materials as thermosetting resins for microelectronic devices

Memory and logic integration for System-in-a-Package

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