Integration of Highly Strained SiGe in Source and Drain with HK and MG for 22 nm Bulk PMOS Transistors

Wang, Guilei; Luo, Jun; Qin, Changliang; Liang, Renrong; Xu, Ya‐Qiong; Liu, Jinbiao; Li, Junfeng; Yin, Huaxiang; Jiang, Yan; Zhu, Huilong; Xu, Jun; Zhao, Chao; Radamson, Henry H.; Ye, Tianchun

doi:10.1186/s11671-017-1908-0

Cited by 25 publications

(14 citation statements)

References 25 publications

(17 reference statements)

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“…The research focuses on the effects of etching process parameters on selection ratio, anisotropy (vertical/lateral etch ratio) and etch morphology. Step 1: Three cycles of SiGe/Si multilayers were grown by using reduced pressure chemical vapor deposition (RPCVD) technique [28,29], and then an oxide-nitride-oxide (ONO) hard mask were grown on the top silicon by applying plasma enhanced chemical vapor deposition (PECVD). In order to examine the film filling and etching performance of inner spacer in detail, Si 0.72 Ge 0.28 stacks with different thicknesses are designed.…”

Section: Methodsmentioning

confidence: 99%

Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors

Zhou

et al. 2020

Nanomaterials

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Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH2F2/CH4/O2/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO2. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.

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Section: Methodsmentioning

confidence: 99%

Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors

Zhou

et al. 2020

Nanomaterials

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“…Step 1: The film of 60 nm Si 0.72 Ge 0.28 was grown by using reduced pressure chemical vapor deposition (RPCVD) technique [35][36][37], and then a 60 nm-thick SiO 2 is grown on the silicon-germanium by plasma enhanced chemical vapor deposition(PECVD).…”

Section: Methodsmentioning

confidence: 99%

A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm

Zhou

et al. 2020

Materials

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Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.

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“…For the sub 10-nm technology node and beyond, the nano-wire device might be one of the promising candidates to obtain better gate control and lower leakage current [63,64,65,66]. In this approach, SiGe/Si multi-layers are grown where either SiGe or Si can be etched selectively to form channel regions for NWs.…”

Section: Sige Epitaxy Of Nano-scaled Transistorsmentioning

confidence: 99%

Miniaturization of CMOS

Radamson

Zhang

et al. 2019

Micromachines

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When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

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Integration of Highly Strained SiGe in Source and Drain with HK and MG for 22 nm Bulk PMOS Transistors

Cited by 25 publications

References 25 publications

Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors

Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors

A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm

Miniaturization of CMOS

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