Integrated test scheduling, test parallelization and TAM design

Abstract

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Test resource partitioning and optimization for SOC designs

“…We have made a comparison between the cost estimation technique proposed in the paper and our previously developed test scheduling and TAM design tool in [7]. We have created a set of test specifications and for each such specification we have estimated the cost and evaluated the cost using the tool in [7].…”

“…We have created a set of test specifications and for each such specification we have estimated the cost and evaluated the cost using the tool in [7]. Note that even though we only created a few test specifications the number of possibilities is high and will increase rapidly for larger designs.…”

“…We will use our proposed system model [7,9], which we partition into a design specification and a test resource specification. A design specification can be modelled as a Each testable unit is viewed as a block and several blocks form a core.…”

“…A test resource specification [7], The placement for each test sources and test sink is given by (x,y) coordinates. For test sources the placement, its maximal allowed bandwidth and the size of the memory are given and for test sinks the placement and the maximal allowed bandwidth are given.…”

“…We have proposed an integrated technique for test scheduling and TAM design minimizing both the test application time and the TAM design while considering test conflicts and power consumption [7,9]. In this paper, we address the creation and optimization of the TRS (test resource specification).…”