Integrated Services Packet Network Using Bus Matrix Switch

Nojima, S.; Tsutsui, Eiichi; Fukuda, Hiroyuki; Hashimoto, Masashi

doi:10.1109/jsac.1987.1146646

Cited by 93 publications

(29 citation statements)

References 4 publications

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“…[11] described a "bus matrix" switch with buffers only at the crosspoints (no input buffers), operating on variable-size packets; we [12] proposed a switch with small crosspoint buffers, large input buffers, and backpressure between them (figures 10-13). Recently, with the availability of technology for single-chip buffered crossbars, a number of groups studied fixed-size-cell buffered crossbars -see e.g.…”

Section: Previous Workmentioning

confidence: 99%

Variable packet size buffered crossbar (CICQ) switches

Katevenis

Passas

Simos

et al. 2004

2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577)

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Abstract-One of the most widely used architectures for packet switches is the crossbar. A special version of a it is the buffered crossbar, where small buffers are associated with the crosspoints. The advantages of this organization, when compared to the unbuffered architecture, is that it needs much simpler and slower scheduling circuits, while it can shape the switched traffic according to a given set of Quality of Service (QoS) criteria in a more efficient way. Furthermore, by supporting variable length packets throughout a buffered crossbar: a) there is no need for segmentation and reassembly circuits, b) no internal speedup is necessary, and c) synchronization between the input and output clock domains is simplified. In this paper we present an architecture, a hardware implementation analysis, and a performance evaluation of such a buffered crossbar. The proposed organization is simple, yet powerful and can be easily implemented using today's technologies. Our evaluation shows that it outperforms most of the existing packet switch architectures, while its hardware cost is kept to a minimum.

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Section: Previous Workmentioning

confidence: 99%

Variable packet size buffered crossbar (CICQ) switches

Katevenis

Passas

Simos

et al. 2004

2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577)

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“…SMB (1,0) SMB (1,3) Input 0 SMB (1,3) Input 0 control information is sent back to Inputs 0 and 3 to indicate the availability of the SMBs. Cells A and G are forwarded to their destined outputs in time slot T + 2.…”

Section: B Shared-memory Crosspoint Buffered Switch With Input-crossmentioning

confidence: 99%

Throughput analysis of shared-memory crosspoint buffered packet switches

Dong

Rojas‐Cessa

2012

IET Commun.

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This paper presents a theoretical throughput analysis of two buffered-crossbar switches, called shared-memory crosspoint buffered (SMCB) switches, in which crosspoint buffers are shared by two or more inputs. In one of the switches, the sharedcrosspoint buffers are dynamically partitioned and assigned to the sharing inputs, and memory is sped up. In the other switch, inputs are arbitrated to determine which of them accesses the shared-crosspoint buffers, and memory speedup is avoided. SMCB switches have been shown to achieve a throughput comparable to that of a combined input-crosspoint buffered (CICB) switch with dedicated crosspoint buffers to each input but, with less memory than a CICB switch. The two analyzed SMCB switches use random selection as the arbitration scheme. We model the states of the shared crosspoint buffers of the two switches using a Markov-modulated process and prove that the throughput of the proposed switches approaches 100% under independent and identically distributed uniform traffic. In addition, we provide numerical evaluations of the derived formulas to show how the throughput approaches asymptotically to 100%.

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“…Figure 2.6 shows an example, the Bus Matrix switch [NoT87], where an address filter (AF) and a FIFO queue replace the crosspoint switch. An incoming cell is broadcast to all attached AFs, but the cell passes through only one AF when their addresses match.…”

Section: Internal or Crosspoint Bufferingmentioning

confidence: 99%

The Folded Hypercube ATM Switches

Park

Davis

2001

Networking — ICN 2001

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Over the past few years, many high performance asynchronous transfer mode (ATM) switches have been proposed. The majority of these switches have high performance but also high hardware complexity. Therefore, there is a need for switch designs with low complexity and high performance. This research proposes three new ATM switches based on the folded hypercube network (FHC). The performance of the three architectures are studied using a network model and simulation. The major performance parameters measured are the cell loss rate and cell delay time through the switch under uniform, normal, and bursty traffic patterns. To guarantee faster switching of time-sensitive cells, the routing algorithm of the three switches uses a priority scheme that gives higher precedence to the time-sensitive cells. Also, an output buffer controller is designed to manage the buffers in a fair manner. The three proposed switch architectures have lower complexity while providing equivalent or better switching performance compared to other more complex ATM switches described in the literature. This research shows a new approach to designing ATM switches by using the FHC as the switching fabric for the first time instead of using the crossbar, multi-path, or Banyan-based switching fabrics.iii DedicationsAfter a long and painful fight against cancer, my grandfather passed away on Christmas Eve, 1999.He deeply wanted to, but was not able to see me receive the doctorate degree. I was blessed to receive his continual love and support for me. I hope he is looking down on me from heaven feeling proud.This dissertation is dedicated to my grandfather, Wookyu Park, in his loving memory.

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Integrated Services Packet Network Using Bus Matrix Switch

Cited by 93 publications

References 4 publications

Variable packet size buffered crossbar (CICQ) switches

Variable packet size buffered crossbar (CICQ) switches

Throughput analysis of shared-memory crosspoint buffered packet switches

The Folded Hypercube ATM Switches

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