Variable packet size buffered crossbar (CICQ) switches

Katevenis, Manolis; Passas, G.; Simos, Dimitris E.; Papaefstathiou, Ioannis; Chrysos, Nikolaos

doi:10.1109/icc.2004.1312669

Cited by 68 publications

(65 citation statements)

References 19 publications

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“…Cell length can be determined by the expected packet length [32], [33]. An appropriate cell length reduces the level of packet segmentation and improves switching performance [11], [34]- [40].…”

Section: F Discussion Of Nonblocking Probability Under Hot Spot and mentioning

confidence: 99%

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Throughput analysis of shared-memory crosspoint buffered packet switches

Dong

Rojas‐Cessa

2012

IET Commun.

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This paper presents a theoretical throughput analysis of two buffered-crossbar switches, called shared-memory crosspoint buffered (SMCB) switches, in which crosspoint buffers are shared by two or more inputs. In one of the switches, the sharedcrosspoint buffers are dynamically partitioned and assigned to the sharing inputs, and memory is sped up. In the other switch, inputs are arbitrated to determine which of them accesses the shared-crosspoint buffers, and memory speedup is avoided. SMCB switches have been shown to achieve a throughput comparable to that of a combined input-crosspoint buffered (CICB) switch with dedicated crosspoint buffers to each input but, with less memory than a CICB switch. The two analyzed SMCB switches use random selection as the arbitration scheme. We model the states of the shared crosspoint buffers of the two switches using a Markov-modulated process and prove that the throughput of the proposed switches approaches 100% under independent and identically distributed uniform traffic. In addition, we provide numerical evaluations of the derived formulas to show how the throughput approaches asymptotically to 100%.

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Section: F Discussion Of Nonblocking Probability Under Hot Spot and mentioning

confidence: 99%

“…This underflow problem was demonstrated under these conditions [12] using the unbalanced traffic model [5], [6]. Buffer underflow was also observed in a buffered crossbar switch but, with internal variable-length segments [11].…”

mentioning

confidence: 99%

Throughput analysis of shared-memory crosspoint buffered packet switches

Dong

Rojas‐Cessa

2012

IET Commun.

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“…There are small buffers at the crosspoints, that enables running independing processors on each input, thus eliminating the need for a centralized scheduler. Besides, scheduling can be performed on variable-size packets, removing the need for packet segmentation and reassembly required in unbuffered crossbars due to synchronous scheduling [15]. Therefore internal speedup is no more required, which in turn facilitates the removal of output buffers.…”

Section: A Cicq Switch Architecturementioning

confidence: 99%

Size-based flow scheduling in a CICQ switch

Divakaran

Anhalt

Altman

et al. 2010

2010 International Conference on High Performance Switching and Routing

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In the context of flow-aware networking, size-based (SB) scheduling policies have been shown to improve response times of small flows, without degrading the performance of large flows. But these differentiating policies are designed for Output-queued (OQ) switch architecture, which is known to have scalability issues. On the other hand, the buffered-crossbar (BX) switch architecture is currently being pursued as a potential next-generation scalable switch architecture. This work looks into the problem of performing SB scheduling in BX switches. In particular, the design goals, with respect to each output port, are (i) to transmit high-priority packet(s) as long as there is at least one present, and (ii) to respect the FIFO order among high-priority packets. In this direction, we propose a CICQ switches using a single PIFO queue at each crosspoint to schedule packets according to the priority assigned. pCICQ-1 switch uses a simple design to guarantee that packet-priorities are respected once they are in the crosspoint queues. But it does not maintain the FIFO order of high-priority packets, besides letting a bounded number low-priority packets to depart through an output, when there are one or more high-priority packets for the same output. To solve this, we propose an enhancement in pCICQ-2 switch, that uses a sequence controller to respect packet-priorities as well as arrival order for high-priority packets.Key-words: scheduling, switch, piority, CICQ Ordonnancement de flux basé sur la taille dans un switch CICQ Résumé : Dans un contexte du traitement par flux, il aété montré que les politiques d'ordonnancement basées sur la taille (size-based (SB)) améliorent le temps de réponse des petits flux, sans dégrader la performance des autres flux. Ces politiques de différenciation sont conues pour des architectures de switch ayant des files d'attente aux ports de sortie (output queued (OQ)), et dont on sait qu'ils sont limités dans le passageà l'échelle. Comme solutionà ce problème de passageà l'échelle, l'architecture de switch avec une matrice de commutationéquipée de buffers aux points d'intersection (buffered crossbar (BX)) est actuellement vue comme pouvantêtre l'architecture des switches de demain. Ce travail examine le problème de réaliser un ordonnancement basé sur la taille dans de tels switches ayant une matrice de commutation avec des buffers. Plus particulièrement, les objectifs au niveau de chaque port de sortie sont (i) de toujours transmettre les paquets prioritaires en premier, et (ii) de respecter l'ordre FIFO entre les paquets prioritaires. Dans ce but, nous proposons un switch CICQ qui utilise une file d'attente PIFOà chaque point d'intersection, afin d'ordonnancer les paquets en fonction de leur priorité. Le switch pCICQ-1 utilise un concept simple pour garantir le respect des priorités des paquets une fois qu'ils ont atteint les files d'attentes aux points d'intersection. Parcontre, il ne maintient pas l'ordre FIFO entre les paquets prioritaires et peut admettre un nombre limité de paqu...

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“…Flow control impedes repeated conflicting decisions by the schedulers, and enforces pipeline-like operation. An additional advantage of independent scheduling is that it can be performed directly on variable-size packets, eliminating the segmentation overhead [9].…”

Section: Introductionmentioning

confidence: 99%

Scheduling in switches with small internal buffers

Chrysos

Katevenis

2005

GLOBECOM '05. IEEE Global Telecommunications Conference, 2005.

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Abstract-Unbuffered crossbars or switching fabrics contain no internal buffers, and function using only input (VOQ) and possibly output queues. Schedulers for such switches are complex, and introduce increased delay at medium loads, because they have to admit at most one cell per input and per output, during each time slot. Buffered crossbars, on the other hand, contain sufficient internal buffering (N 2 buffers) to allow independent schedulers to concurrently forward packets to the same output from any number of inputs. These architectures represent the two extremes in a range of solutions, which we examine here; although intermediate points in this range are of reduced practical interest for crossbars, they are nevertheless quite interesting for switching fabrics, and they may be of interest for optical switches. We find that tolerating two cells per-output per timeslot, using small buffers inside the switch or fabric, suffices for independent and efficient scheduling. First, we introduce a novel "request-grant" credit protocol, enabling N inputs to share a small switch buffer. Then, we apply this protocol to a switch with N such buffers, one per output, and we consider the resulting scheduling problem. Interestingly, this looks like unbuffered crossbar schedulers, but it is much simpler because it comprises independent, single-resource schedulers that can be pipelined. We show that individual buffer sizes do not need to grow, neither with switch size nor with propagation delay. Through simulations, we study performance as a function of the number of cells allowed per-output per-time-slot. For one cell, the switch performs very close to the iSLIP unbuffered crossbar with one iteration. For more cells, performance improves quickly; for 12 cells, packet delay under (smooth) uniform load is practically as low as ideal output queueing. Under unbalanced load, throughput is superior to buffered crossbars, due to better buffer sharing.

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Variable packet size buffered crossbar (CICQ) switches

Cited by 68 publications

References 19 publications

Throughput analysis of shared-memory crosspoint buffered packet switches

Throughput analysis of shared-memory crosspoint buffered packet switches

Size-based flow scheduling in a CICQ switch

Scheduling in switches with small internal buffers

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