Integrated retiming and placement for field programmable gate arrays

Abstract

Retiming is a synchronous circuit transformation that can optimize the delay of a synchronous circuit by moving registers across combinational circuit elements. The combinational structure remains unchanged and the observable behavior of the circuit is identical to the original.In this paper, we address the problem of applying retiming techniques to circuits implemented in Field Programmable Gate Arrays (FPGAs). FPGAs contain prefabricated and configurable routing elements that allow us to easily implement a variety of circuits. However this interconnect contributes greatly to the overall delay in the implemented circuit. If a circuit is retimed prior to the placement and routing phases of the CAD flow, then it has no information about the delays introduced by the configurable interconnect. Our fundamental experiment is to determine whether there are any gains in tightly coupling retiming and placement so that the retiming algorithm has some estimate of the routing delays.Specifically, we introduce a post-placement retiming algorithm that understands how to take advantage of FPGA architectural features. This retiming algorithm may introduce extra registers into the circuit. These new registers need to be placed in some location in the FPGA. Retiming register placement is accomplished by a novel incremental clustering and placement algorithm. The incremental algorithm builds upon the placement of the non-retimed circuit to intelligently sift in the newly-introduced registers.In addition, we explore making the placement algorithms "retiming aware." These placement algorithms try to place logic blocks in such a way that the subsequent retiming produces better speed results. These techniques include the identification of retiming-critical cycles during placement.Our experiments show that the integration of retiming with placement results in 19% better clock periods in comparison to the application of retiming before the place and route steps.

Simultaneous Retiming and Placement for Pipelined Netlists

“…Unfortunately, any direct comparison to the Singh and Brown toolflow [10] is relatively difficult. We do not have access to their code base and the paper is fairly vague regarding their exact testing conditions.…”

“…The most encouraging work to date on integrated FPGA placement and retiming is [10]. Much like the work in [3], they use a three-phase approach that begins with a specialized timing-driven simulated annealing placement.…”

Latch-Based Performance Optimization for FPGAs

“…VPR gauges the criticality of a connection using its slack ratio, which is the ratio of the worst-case path delay through a connection, to the current critical path delay. We altered VPR's criticality notion to drive place and route using cycle-slacks [19], [23]. The cycle-slack ratio of a connection is the cycle ratio of any cycle that uses the connection, to the current MCR of the design.…”

Architecture and Synthesis for On-Chip Multicycle Communication

“…There have been some efforts to address the problem of multicycle on-chip communication for synchronous designs. Most of them are at the gate level to perform retiming with placement or floorplanning [3], [5], [6], [25] to alleviate the performance degradation caused by long interconnects. Although the benefit of applying these methods can be significant, exploring multicycle communication during logic synthesis has a severe limitation, as the minimum clock period that can be achieved by logic optimization is bounded by the maximum delay-to-register (DR) ratio of the loops in the circuit [4], [21].…”