Integrated Output Matching Networks for Class–J/J<sup>−1</sup> Power Amplifiers

Alizadeh, Amirreza; Hassanzadehyamchi, Saleh; Medi, Ali

doi:10.1109/tcsi.2019.2912007

Cited by 19 publications

(8 citation statements)

References 19 publications

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“…By calculating and adjusting the values of Tl 1 , Tl 2 and C 1 , Г omn at second harmonic achieves the optimal efficiency region in Figure 9. [20][21][22][23][24]27 In addition, Tl 3 and C bp can be used as a bias network for the final stage device. Once the topology of second harmonic matching has been obtained, its A matrix [A 2f0 ] as well as Г omn@2f0 can be calculated.…”

Section: Output Matching Network Designmentioning

confidence: 99%

“…In Figure 10, the topology in the red box is second harmonic matching network, in which Tl 3 and C bp provide a short point for second harmonic. By calculating and adjusting the values of Tl 1 , Tl 2 and C 1 , Г omn at second harmonic achieves the optimal efficiency region in Figure 9 20‐24,27 . In addition, Tl 3 and C bp can be used as a bias network for the final stage device.…”

Section: Power Amplifier Matching Network Designmentioning

confidence: 99%

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A 18‐23 GHz power amplifier design using approximate optimal impedance region approach for satellite downlink

Zhao

et al. 2021

Int J RF Microw Comput Aided Eng

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This paper presents the design procedure of a K-band 0.1 μm GaAs pseudomorphic high electron mobility transistors (pHEMT) monolithic microwave integrated circuit (MMIC) for satellite communication downlinks. The method focuses on the selection and design of the matching network (MN) by applying the Approximate Optimal Impedance Region (AOIR) approach which is a composition of simple mathematical constraints. The AOIR approach overcomes the drawbacks of traditional MN design method which cannot control the reflection coefficient trajectory of the MN precisely. The method formulates the constraints through symbolic-graphic combinations with integrated functions of computer-aided design (CAD) tools. The impedance transformation trajectory of MN is combined to reduce the mismatch and the insertion loss using equations with multiple mathematical constraints to realize the automatic selection of the MN's topology. The AOIR method fully considers the underutilized characteristics of power amplifier (PA) and to maximize its performance in a balanced manner. The MMIC, was designed using the proposed technique, operates in 18 GHz-23 GHz with a gain of 27 dB and has an average P −1 dB of 27 dBm and PAE of 38% under the continuous wave (CW) drive signal.

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Section: Output Matching Network Designmentioning

confidence: 99%

Section: Power Amplifier Matching Network Designmentioning

confidence: 99%

A 18‐23 GHz power amplifier design using approximate optimal impedance region approach for satellite downlink

Zhao

et al. 2021

Int J RF Microw Comput Aided Eng

View full text Add to dashboard Cite

show abstract

“…According to class-J power amplifiers theory, the drain efficiency is up to 78.5% as ideal class-B. [15][16][17][18][19][20] Their voltage and current waveforms are half sine waves. The second harmonic impedance only has a reactance value.…”

Section: Theoretical Analysismentioning

confidence: 99%

“…According to class‐J power amplifiers theory, the drain efficiency is up to 78.5% as ideal class‐B . Their voltage and current waveforms are half sine waves.…”

Section: Theoretical Analysismentioning

confidence: 99%

“…The second harmonic impedance only has a reactance value. The expressions of the fundamental and second harmonic impedance of class‐J power amplifiers are given

Z_{j, 1} = R_{opt} ((), 1 + italicjγ) - 1 \leq γ \leq 1,

Z_{j, 2} = - j \frac{3 π}{8} R_{opt} γ - 1 \leq γ \leq 1,

where R opt is optimal load impedance. Fundamental and second output impedances are Z j ,1 and Z j ,2 respectively.…”

Section: Theoretical Analysismentioning

confidence: 99%

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A broadband class‐F/J hybrid power amplifier

Guo

Cheng

et al. 2020

Micro & Optical Tech Letters

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This article proposes a new broadband high-efficiency hybrid power amplifier (PA) design methodology that combines a class-J PA with a class-F PA using GaN HEMT CGH40010F. Multifrequency harmonic control method is employed to achieve harmonic matching network for increasing the bandwidth of the PA. In order to validate the effectiveness of the proposed method, a 1 to 2.8 GHz broadband class F/J PA is designed and fabricated. The simulation and measurement results show that the saturated output power is 40 to 42 dBm, the gain is over 10 dB and the drain efficiency is 65% to 71% at the frequency of 1 to 2.8 GHz.

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Design of an RF output Class JJ⁻¹ Doherty power amplifier using post‐matching varactor diodes for configurable IoT transmitters

Kumar

Kanaujia

2022

Circuit Theory & Apps

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In this paper, a Doherty power amplifier (DPA) based on Class-J power amplifier (PA) and Class-J À1 PA is proposed for configurable Internet of things (IoT) transmitters. A post-matching structure is used to achieve wider bandwidth performance, high efficiency, and power gain flatness. Different drain biases on the main and peaking devices are used to perform asymmetric operations. The proposed DPA structure achieves 62.4% power-added efficiency (PAE) with a maximum output range of 37.38-38.20 dBm for the frequency band of 5.1-5.8 GHz and a power gain range of 13.24-12.24 dB. It has a maximum drain efficiency of 42.7%-51.5% at a back-off power level of 9 dB. In order to validate the linearity of the proposed design, an analysis of the adjacent channel leakage ratio (ACLR) for various gate-biased voltage operations is performed. The microchip occupies a compact die area of 2.1 mm Â 1.2 mm, which is fabricated with GaAs 0.25 μm PHEMT to validate the enhanced broadband characteristics of the proposed configuration. Compared to the existing DPAs, the proposed DPA exhibits higher efficiency, output power, and compact size. K E Y W O R D SDoherty power amplifier (DPA), gallium arsenide (GaAs), post-matching network, poweradded efficiency (PAE), stacked FET

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Integrated Output Matching Networks for Class–J/J⁻¹ Power Amplifiers

Cited by 19 publications

References 19 publications

A 18‐23 GHz power amplifier design using approximate optimal impedance region approach for satellite downlink

A 18‐23 GHz power amplifier design using approximate optimal impedance region approach for satellite downlink

A broadband class‐F/J hybrid power amplifier

Design of an RF output Class JJ⁻¹ Doherty power amplifier using post‐matching varactor diodes for configurable IoT transmitters

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Integrated Output Matching Networks for Class–J/J−1 Power Amplifiers

Cited by 19 publications

References 19 publications

A 18‐23 GHz power amplifier design using approximate optimal impedance region approach for satellite downlink

A 18‐23 GHz power amplifier design using approximate optimal impedance region approach for satellite downlink

A broadband class‐F/J hybrid power amplifier

Design of an RF output Class JJ−1 Doherty power amplifier using post‐matching varactor diodes for configurable IoT transmitters

Contact Info

Product

Resources

About

Integrated Output Matching Networks for Class–J/J⁻¹ Power Amplifiers

Design of an RF output Class JJ⁻¹ Doherty power amplifier using post‐matching varactor diodes for configurable IoT transmitters