2013
DOI: 10.1109/jphot.2013.2280519
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Integrated Optical Delay Lines for Time-Division Multiplexers

Abstract: In this paper, we present a study of integrated optical delay lines (DLs) for application in optical time-division multiplexers. The investigated DLs are formed by spirally folded waveguides. The components were designed in a generic approach and fabricated in multi-project wafer runs on an InP-based platform. The design process and rules, together with characterization results of test structures, are discussed. Static and dynamic measurements were performed for verification of the DLs' performance in the wave… Show more

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Cited by 22 publications
(9 citation statements)
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“…Errorfree operation for both the variable optical buffer and the TSI is demonstrated with 10Gb/s NRZ data packets, revealing power penalty, depending on the integrated delay line used, from 3dB to 5dB. The demonstrated optical delay linebased buffering and TSI configurations report the highest delay efficiency values with respect to required footprint of the delay lines, offering a delay efficiency of 2.6ns/mm 2 that is two orders of magnitude higher than in respective demonstrations so far [7][8][9][10][11][12] with the highest delay being 17.2ns.…”
Section: Introductionmentioning
confidence: 84%
See 1 more Smart Citation
“…Errorfree operation for both the variable optical buffer and the TSI is demonstrated with 10Gb/s NRZ data packets, revealing power penalty, depending on the integrated delay line used, from 3dB to 5dB. The demonstrated optical delay linebased buffering and TSI configurations report the highest delay efficiency values with respect to required footprint of the delay lines, offering a delay efficiency of 2.6ns/mm 2 that is two orders of magnitude higher than in respective demonstrations so far [7][8][9][10][11][12] with the highest delay being 17.2ns.…”
Section: Introductionmentioning
confidence: 84%
“…Integrated delay lines have been demonstrated via several alternative integration platforms, exploiting asymmetrical MZIs [6], ring resonators [7], Silica on Silicon integration [8][9], thermo-optics switches on Si3N4 platform [10], polymer waveguides [11] and the InP platform [12]. Nevertheless, most of these demonstrations offer tunable delay in the range of a few hundred ps [6,7,11], limiting their functionality in terms of packet re-arrangement.…”
Section: Introductionmentioning
confidence: 99%
“…As a result, many photonic ICs for various applications, e.g. for telecommunications and sensing, have been designed, fabricated and characterized, which proved their very good overall performance [5], [13]- [19].…”
Section: Fabrication Technologymentioning
confidence: 99%
“…The second subsystem is a variable optical delay-line buffer and Time-slot Interchanger module utilizing a set of three on-chip um scale Si-based integrated delay lines with low propagation loss and two, differentially-biased, SOA-MZI based wavelength converters (WC) [26]. The chip-scale SOI delay bank offers variable optical delay that ranges from 6.5 ns to 17.2 ns with a record-high on-chip delay versus footprint efficiency of 2.6 ns/mm 2 , improved by almost one order of magnitude compared to the 0.38 ns/mm 2 state of the art implementations, featuring at least 10 ns on-chip delay [27][28][29][30][31][32][33][34]. This integrated variable SOI-based delay bank along with two WCs are utilized for the demonstration of a variable optical buffering scheme at 10 Gb/s, while the largest on-chip delay line of 17.2 ns is shown to perform successfully also in a 10 Gb/s optical TSI demonstration that uses two additional delay lines formed by fibers and two WC modules.…”
Section: Introductionmentioning
confidence: 99%