Integrated CMOS-Based Sensor Array for Mechanical Stress Mapping

Ruther, Patrick; Bartholomeyczik, J.; Kibbel, Steffen; Schelb, T.; Gieschke, P.; Oliver, Paul

doi:10.1109/icsens.2007.355825

Cited by 9 publications

(4 citation statements)

References 7 publications

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“…A p+-guard ring is placed around the NMOS sensors shown in Figs. 1 and (d) have non-conducting central holes enhancing their sensitivity [2,7]. The most important geometrical parameters are listed in Table 1.…”

Section: Piezo-fet Stress Sensors Design and Fabricationmentioning

confidence: 99%

“…In order to increase the resolution of die stress maps, CMOS chips with integrated circuitry have been designed, e.g. using 32 octagonal nwell resistors [2] and 512 current mirror type piezoresistive metal oxide semiconductor field effect transistors (MOSFETs) [3] as stress sensors. To integrate larger numbers of stress sensors in mixed-signal CMOS chips, piezo-FETs are superior to diffused piezoresistors since the gate contact serves as an intrinsic switch.…”

Section: Introductionmentioning

confidence: 99%

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CMOS Integrated Stress Mapping Chips with 32 N-Type or P-Type Piezoresistive Field Effect Transistors

Gieschke

Nurcahyo

Herrmann

et al. 2009

2009 IEEE 22nd International Conference on Micro Electro Mechanical Systems

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This paper reports a novel generation of CMOS stress mapping chips comprising 32 square field effect transistors (FET) with four source/drain contacts (piezoFETs) exploiting the shear piezoresistive effect in n-type (NMOS) or p-type (PMOS) inversion layers. The sensor chips with a total die area of 2.5 x 2 mm2 are integrated with analog circuitry and digital logic. When exposed to homogenous shear or normal stress, all 32 integrated stress sensors show a linear response in excellent agreement with theoretical predictions and exhibit identical stress sensitivities. Piezo-FETs fabricated as separate devices are characterized with respect to stress sensitivity, intrinsic offset, and noise behavior. Stress sensitivities are enhanced by incorporating a central hole into the piezo-FETs. Sensitivities of -448 iV/(V MPa) and 477 iV/(V MPa) were measured for NMOS and PMOS devices, respectively.

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Section: Piezo-fet Stress Sensors Design and Fabricationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

CMOS Integrated Stress Mapping Chips with 32 N-Type or P-Type Piezoresistive Field Effect Transistors

Gieschke

Nurcahyo

Herrmann

et al. 2009

2009 IEEE 22nd International Conference on Micro Electro Mechanical Systems

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“…Such sensor rosettes occupy significant area and hence result in relatively large sampling distances and limited sensor array sizes. Similar limitations hamper other, CMOS multiplexer based, test chips as for instance reported in [5][6][7][8][9]. The array-based test structure implementation chosen for the work described in this paper combines learnings from prior art array-style test chips, many of which were discussed before at ICMTS e.g.…”

Section: Introductionmentioning

confidence: 99%

Design and use of an array-based test structure to characterize mechanical stress effects caused by WLCSP solder bumps

Tuinhout

Dalen²

2016

2016 International Conference on Microelectronic Test Structures (ICMTS)

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this paper discusses a 2100-DUT-array based test structure approach for high-resolution characterization of spatial mechanical stress distributions that are attributable to wafer level chip scale package solder bumps. DUT cell layout requirements, array implementation, measurement approach, and some data analysis challenges are reviewed in detail. Several examples of solder bump induced mobility variation illustrate the value of these test structures.

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“…In ref. [1] a CMOS integrated stress sensor for packaged integrated circuit dies is presented, and ref. [2] shows a van der Pauw structure used for stress sensing.…”

Section: Introductionmentioning

confidence: 99%

Realtime 3D Stress Measurement in Curing Epoxy Packaging

Richter

Hyldgård

Birkelund

et al. 2007

TRANSDUCERS 2007 - 2007 International Solid-State Sensors, Actuators and Microsystems Conference

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This paper presents a novel method to characterize stress in microsystem packaging. A circular p-type piezoresistor is implemented on a (001) silicon chip. We use the circular stress sensor to determine the packaging induced stress in a polystyrene tube filled with epoxy. The epoxy curing process is monitored by stress measurements. From the stress measurements we conclude that the epoxy cures in 8 hours at room temperature. We find the difference in in-plane normal stresses to be σ xx -σ yy =6.7 MPa and (σ xx +σ yy -0.4σ zz )=232 MPa.

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Integrated CMOS-Based Sensor Array for Mechanical Stress Mapping

Cited by 9 publications

References 7 publications

CMOS Integrated Stress Mapping Chips with 32 N-Type or P-Type Piezoresistive Field Effect Transistors

CMOS Integrated Stress Mapping Chips with 32 N-Type or P-Type Piezoresistive Field Effect Transistors

Design and use of an array-based test structure to characterize mechanical stress effects caused by WLCSP solder bumps

Realtime 3D Stress Measurement in Curing Epoxy Packaging

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