Integrated circuit implementation of fuzzy controllers

Abstract

This paper presents mixed-signal current-mode CMOS circuits to implement programmable fuzzy controllers that perform the singleton or zero-order Sugeno's method. Design equations to characterize these circuits are provided to explain the precision and speed that they offer. This analysis is illustrated with the experimental results of prototypes integrated in standard CMOS technologies. These tests show that an equivalent precision of 6 bits is achieved. The connection of these blocks according to a proposed architecture allows fuzzy chips with low silicon area whose inference speed is in the range of 2 Mega FLIPS (fuzzy logic inferences per second).

A highly accurate fully programmable fuzzifier in current mode approach

“…The most important characteristics of a fuzzifier that a designer should be considered are programmability and accuracy. After the fuzzifier published by Huertas [7], Mottaghi et al improved their circuit with some modifications to make it programmable with different slopes of ascending and descending parts [4]. The other current mode fuzzifier circuits have the same structures.…”

A modular programmable CMOS analog fuzzy controller chip

“…6(a) shows, so that the rule block has only one input. Another current-mode maximum circuit based also on Lazzaro's was proposed in [31] and used in [14]. It connects the output transistor as a diode, removes the current source and connects the drains of the top transistors to a common node which is the output node.…”

“…The last error is due to dc voltage mismatching between the input and output nodes of the pMOS current mirror driving the minimum input cell, (14) where is the equivalent Early voltage of the pMOST's. This error can be attenuated by proper setting of the bias voltage of the cascode transistor For optimum attenuation, this voltage should be different for different input values.…”

“…5, where we assume that the two diode-connected transistors have the same aspect ratio, (16) and is a reference current. This choice reduces the relative error in (14) to around 0.5%-negligible at the system level.…”

“…There are three main approaches for the analog implementation of (22): 1) using an extension of Mead [33] followeraggregation circuit with weighting capability [16], [37]; 2) using weighting-plus-division circuits [14], [22], [35] [36]; and 3) using normalization-plus-weighting circuits [9], [25], [28]. The first uses an elegant circuit concept, see Fig.…”