In this paper, an ultrafast steady-state genetic algorithm processor (GAP) is presented. Due to the heavy computational load of genetic algorithms (GAs), they usually take a long time to find optimum solutions. Hardware implementation is a significant approach to overcome the problem by speeding up the GAs procedure. Hence, we designed a digital CMOS implementation of GA in [Formula: see text] process. The proposed processor is not bounded to a specific application. Indeed, it is a general-purpose processor, which is capable of performing optimization in any possible application. Utilizing speed-boosting techniques, such as pipeline scheme, parallel coarse-grained processing, parallel fitness computation, parallel selection of parents, dual-population scheme, and support for pipelined fitness computation, the proposed processor significantly reduces the processing time. Furthermore, by relying on a built-in discard operator the proposed hardware may be used in constrained problems that are very common in control applications. In the proposed design, a large search space is achievable through the bit string length extension of individuals in the genetic population by connecting the 32-bit GAPs. In addition, the proposed processor supports parallel processing, in which the GAs procedure can be run on several connected processors simultaneously.
We present the procedure for designing a high speed and low power alloptical analog to digital converter (AO-ADC), by integrating InGaAsP semiconductor optical amplifier (SOA) with InP based photonic crystal (PhC) drop filters. The self-phase modulation in the SOA can shift the frequency of the Gaussian input pulse. The two output PhC based drop filters are designed to appropriately code the frequency-shifted analog signals by the SOA, converting them to four desired digital output levels. Our numerical results show that in an appropriately designed AO-ADC, the center wavelength (1572 nm) of an amplitude modulated Gaussian pulse of 1.8 ps width and 1.56 pJ energy can be shifted by 6.7 nm, by the SOA, and then be quantized and coded to four digital levels (00, 01, 10, and 11). The two point-defect PhC drop filters, compensating the effect of the frequency shift by SOA, minimize the AO-ADC integral and differential nonlinearity errors.
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