High-Speed General Purpose Genetic Algorithm Processor

Abstract

In this paper, an ultrafast steady-state genetic algorithm processor (GAP) is presented. Due to the heavy computational load of genetic algorithms (GAs), they usually take a long time to find optimum solutions. Hardware implementation is a significant approach to overcome the problem by speeding up the GAs procedure. Hence, we designed a digital CMOS implementation of GA in [Formula: see text] process. The proposed processor is not bounded to a specific application. Indeed, it is a general-purpose processor, which is capable of performing optimization in any possible application. Utilizing speed-boosting techniques, such as pipeline scheme, parallel coarse-grained processing, parallel fitness computation, parallel selection of parents, dual-population scheme, and support for pipelined fitness computation, the proposed processor significantly reduces the processing time. Furthermore, by relying on a built-in discard operator the proposed hardware may be used in constrained problems that are very common in control applications. In the proposed design, a large search space is achievable through the bit string length extension of individuals in the genetic population by connecting the 32-bit GAPs. In addition, the proposed processor supports parallel processing, in which the GAs procedure can be run on several connected processors simultaneously.

AI-based modeling and data-driven evaluation for smart manufacturing processes

“…GA consists of different phases, i.e. parent selection, crossover, mutation, and creating final population (the selected features) [17]. Parent Selection is a crucial part of GA and consists of a finite repetition of different operations, i.e., selection of parent strings, recombination, and mutation.…”

Usage of swarm intelligence strategies during projection of parallel neuroevolution methods for neuromodel synthesis

“…A number of previous works [6][7][8] identify typical problems that arise in the design of parallel ANN synthesis based on evolutionary strategies. Usually, such problems are associated either with architectural features of the system, or with certain difficulties in determining free parameters of methods.…”

“…So, sufficiently large amounts of information can significantly reduce the speed of work. Therefore, for example, it is possible to distribute certain initializationrelated steps directly between threads [6,7].…”

FPGA Implementation of Crossover Module of Genetic Algorithm

“…In Reference [7], a GA engine is proposed that supports one-point and two-point crossovers. The proposed GA processor in Reference [8] has three methods of crossover including one-point, two-point, and uniform crossovers. A parallel GA system on four Virtex-6 FPGA is proposed in Reference [9].…”