Instruction set extensions for software defined radio

Mamidi, Suman; Blem, Emily; Schulte, Michael; Glossner, John; Iancu, Daniel; Iancu, Andrei; Moudgill, Mayan; Jinturkar, Sanjay

doi:10.1016/j.micpro.2009.02.005

Cited by 8 publications

(4 citation statements)

References 15 publications

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“…Each core is multithreaded, runs eight threads simultaneously [15], and is paritioned into three units, as shown in Figure 3. These are an instruction fetch and branch unit, an integer and load/store unit, and a SIMD vector unit.…”

Section: Sb3010 Sdr Platformmentioning

confidence: 99%

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Instruction set extensions for the advanced encryption standard on a multithreaded software defined radio platform

Jenkins¹,

Schulte²,

Glossner³

2010

IJHPSA

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Software-defined radio (SDR) is an emerging technology that facilitates having multiple wireless communication protocols on one device. Previous work has shown that current W-CDMA, GPS, GSM, and WiMAX applications can run on this class of device while consuming significant processing power. Next generation wireless networks require speeds in excess of 50Mbps. Some of the fastest AES software implementations only achieve 20Mbps on our reference platform. In order to have secure software-defined radio, the security processing gap must be addressed. This paper presents instruction set architecture (ISA) extensions for the Sandblaster DSP. The Sandblaster DSP is a multithreaded processor for SDR that issues multiple operations each cycle and supports vector operations.

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Section: Sb3010 Sdr Platformmentioning

confidence: 99%

“…To support eight hardware threads, the architecture uses a uniquire form of interleaved multithreading (IMT) known as token thread triggering (T 3 ) [15]. Each thread occupies one pipeline stage per cycle.…”

Section: Sb3010 Sdr Platformmentioning

confidence: 99%

Instruction set extensions for the advanced encryption standard on a multithreaded software defined radio platform

Jenkins¹,

Schulte²,

Glossner³

2010

IJHPSA

Self Cite

View full text Add to dashboard Cite

show abstract

“…The kernel operations of N-point FFT ( ), such as the first 9 iterations butterfly operations of 1024-point FFT, can be organized into operation sequences using the shuffle networks (the twiddle factors be generated from lookup table), decreasing the executing time. To support the kernel algorithms of the next generation wireless communication systems, several specific instructions are introduced in MPEs, such as butterfly [16], Add-Compare-Select, and so on. When they work cognately, the addresses of cluster1~cluster3 will be calculated by adding HOPLENREG*index and the address generated by C0_AGU0, index is the related cluster index number.…”

Section: B Sc-tdm Bus Systemmentioning

confidence: 99%

Domain specific architecture for next generation wireless communication

Zhang¹,

Liu²,

Zhao³

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communication domain specific processor, and then proposes a novel processor architecture for the next generation wireless communication named GAEA using this design flow. GAEA is a shared memory multi-core SoC based on Software Controlled Time Division Multiplexing Bus, with which programmers can easily explore memory-level parallelism of applications by proper instructions and scheduling algorithms. MPE, which is the kernel component of GAEA, adopts hybrid parallel processing scheme to explore instruction-level and data-level parallelism. The pipeline and instruction set of GAEA are also optimized for the next generation wireless communication systems. The evaluation and implementation results show that GAEA architecture is suitable for the next generation wireless communication systems.I.

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“…This can be transfer among the hard and reliable decision. Through this approach the parameters like state, code and iterations are evaluated [18][19][20]. The decoding schemes have some demerits like complexity, power consumption, computational burden, etc.…”

Section: Introductionmentioning

confidence: 99%

Application of Fixed Point Turbo Decoding Algorithm for Throughput Enhancement of SISO Parallel Advanced LTE Turbo Decoders

Madhukumar¹,

Ramu²,

Veerasamy³

et al. 2017

IJIES

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Turbo decoding for the advanced 4GPP-LTE wireless communication standard is the most challenging technique in terms of computational complexity and power consumption of corresponding cellular devices. The standard VLSI implementation of turbo decoder requires memory, latency, area, power, and throughput. These particularities cannot tolerate in some applications as well as the previous method of floating point has some pitfalls due to this; the performance is degraded. The novel fixed point technique for SISO parallel advanced long-term evolution turbo decoders with new hard-wried 6144 bit interleaver is proposed here to achieve the specification. The major contribution of the planned methodology is the enhancement of throughput in parallel SISO decoders by eliminating the critical data path problem in floating point method. The signal to noise ratio is calculated to reduce the power consumption, and zero state metrics are used to eliminate the bit error rate. The designed algorithms are used to enhance the error correction capacity.

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Instruction set extensions for software defined radio

Cited by 8 publications

References 15 publications

Instruction set extensions for the advanced encryption standard on a multithreaded software defined radio platform

Instruction set extensions for the advanced encryption standard on a multithreaded software defined radio platform

Domain specific architecture for next generation wireless communication

Application of Fixed Point Turbo Decoding Algorithm for Throughput Enhancement of SISO Parallel Advanced LTE Turbo Decoders

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