Domain specific architecture for next generation wireless communication

Zhang, Botao; Liu, Hengzhu; Zhao, Haitao; Mo, None Fangzheng; Chen, Ting

doi:10.1109/date.2010.5457034

Cited by 3 publications

(1 citation statement)

References 12 publications

(13 reference statements)

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“…In [29] a radix-4/2 butterfly structure is adopted for exploring the parallelism in the FFT calculation, but it requires more memory accesses. In [30], four VLIW vias and four tracks in the SIMD architecture are adopted, with different data shuffling modes to improve the FFT transfer rate, aiming to reduce energy consumption.…”

Section: Application Example: Fft Synthesismentioning

confidence: 99%

ASIPAMPIUM: An Efficient ASIP Generator for Low Power Applications

et al. 2023

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The adoption of customized ASIPs (Application Specific Instruction Set Processors) in embedded circuits is an important alternative for optimizing power consumption, silicon area, or processing performance according to the design requirements. The processor is implemented specifically for the target application, which allows the hardware customization in terms of instruction set architecture, data word length, memory size, and parallelism. This work describes an EDA tool for the semi-automatic development of ASIPs named ASIPAMPIUM. The strategy is to provide a set of integrated tools to interpret and generate a customized hardware for a given target application, including compilation, simulation, and hardware synthesis. From the C code description of the application, the tool returns a synthesizable hardware description of the processor. The proposed methodology is based on the adaptation of a new customizable microprocessor called PAMPIUM, which can be optimized in terms of silicon area, power consumption, or processing performance according to the target application. The ASIPAMPIUM tool provides a series of simulated data to the designer in order to identify optimization strategies in both software and hardware domains. We show the results for the implementation of an FFT algorithm using the proposed methodology, which achieved best results in terms of silicon area and energy consumption compared to other works described in the literature for both FPGA and silicon implementation. Moreover, measurement results of the implementation in silicon of a dedicated ASIP for interfacing with six sensors in real-time, including three I2C, an SPI, and an RS-232 interfaces, demonstrate the complete design flow, from the C code program to physical implementation and characterization. Aside from providing a short design time, the ASIPAMPIUM tool also affords a simple and intuitive design flow, allowing the designer to deal with different design trade-offs and objectives.

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Section: Application Example: Fft Synthesismentioning

confidence: 99%

ASIPAMPIUM: An Efficient ASIP Generator for Low Power Applications

et al. 2023

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Rapid prototype and implementation of a high-throughput and flexible FFT ASIP based on LISA 2.0

Chen

Pan

Liu

et al. 2014

Fifteenth International Symposium on Quality Electronic Design

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This paper presents a highly efficient machine description language LISA for application specific instructionset processor (ASIP) architecture exploration, software tools design, system verification and design implementation. The proposed design flow enables a rapid prototyping and evaluation of different architectures, reduces the design time and human effort with regard to traditional design methodologies. A case study for parallel FFT algorithm is demonstrated in this work. We proposed a scalable butterfly processing structure with fixed shuffling mode between stages. Besides, resource sharing and an efficient vector address generation mechanism are adopted to reduce the hardware complexity and power dissipation. Simulation and synthesis results show that our FFT-ASIP achieves a higher energy-efficiency and flexibility than other works, and the area cost is low.

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