Rapid prototype and implementation of a high-throughput and flexible FFT ASIP based on LISA 2.0

Chen, Ting; Pan, Xiaowei; Liu, Hengzhu; Wu, Tiebin

doi:10.1109/isqed.2014.6783393

Cited by 2 publications

(2 citation statements)

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“…The work presented by [13] uses LISA 2.0 to generate the hardware. The main goal of LISA is to detect the details of the processor architecture implementation and to model it to a higher level of abstraction.…”

Section: Related Workmentioning

confidence: 99%

“…It is also possible to compare the results obtained by the physical synthesis of the PAMPIUM_M and PAMPIUM_S in 180 nm fabrication technology with other state-of-theart works in the literature. The work described in [13] presents a hardware description language of the LISA machine for the implementation of an ASIP. Using software tools for design, system verification, and implementation, the proposed design flow allows prototyping and testing, aiming to reduce design time and human effort with respect to traditional design methodologies.…”

Section: Application Example: Fft Synthesismentioning

confidence: 99%

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ASIPAMPIUM: An Efficient ASIP Generator for Low Power Applications

et al. 2023

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The adoption of customized ASIPs (Application Specific Instruction Set Processors) in embedded circuits is an important alternative for optimizing power consumption, silicon area, or processing performance according to the design requirements. The processor is implemented specifically for the target application, which allows the hardware customization in terms of instruction set architecture, data word length, memory size, and parallelism. This work describes an EDA tool for the semi-automatic development of ASIPs named ASIPAMPIUM. The strategy is to provide a set of integrated tools to interpret and generate a customized hardware for a given target application, including compilation, simulation, and hardware synthesis. From the C code description of the application, the tool returns a synthesizable hardware description of the processor. The proposed methodology is based on the adaptation of a new customizable microprocessor called PAMPIUM, which can be optimized in terms of silicon area, power consumption, or processing performance according to the target application. The ASIPAMPIUM tool provides a series of simulated data to the designer in order to identify optimization strategies in both software and hardware domains. We show the results for the implementation of an FFT algorithm using the proposed methodology, which achieved best results in terms of silicon area and energy consumption compared to other works described in the literature for both FPGA and silicon implementation. Moreover, measurement results of the implementation in silicon of a dedicated ASIP for interfacing with six sensors in real-time, including three I2C, an SPI, and an RS-232 interfaces, demonstrate the complete design flow, from the C code program to physical implementation and characterization. Aside from providing a short design time, the ASIPAMPIUM tool also affords a simple and intuitive design flow, allowing the designer to deal with different design trade-offs and objectives.

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Section: Related Workmentioning

confidence: 99%

Section: Application Example: Fft Synthesismentioning

confidence: 99%