ASIP for 5G and Beyond: Opportunities and Vision

Shahabuddin, Shahriar; Mämmelä, Aarne; Juntti, Markku; Silvén, Olli

doi:10.1109/tcsii.2021.3050785

Cited by 7 publications

(4 citation statements)

References 69 publications

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“…[36] proposes a custom fast fourier transformation (FFT) instruction for increased throughput on orthogonal frequency division multiplexing (OFDM)-based communication standards. Opportunities for ASIPs in 5G networks are surveyed in [37]. The authors also mention ASIPs for ML acceleration as a future direction in 5G applications.…”

Section: B Isa Extensions For Domain Specializationmentioning

confidence: 99%

“…The vector processor supports floating-point operations, offering more numerical precision than needed by our applications, resulting in an increased area cost and lower energy efficiency than our RRM ASIP. The hardwired accelerator provides the highest energy efficiency, however, hardwired accelerators are not flexible to adapt to the rapidly changing RRM field as new algorithms would require a costly HW redesign [37]. Even though our implementation focuses on 16 bits instead of 8 bits, on a single-ASIP system, we achieve >2× higher OP/cycle than a comparable commercially available dual-issue core (STM32H743).…”

Section: Comparison With Related Workmentioning

confidence: 99%

See 1 more Smart Citation

RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures

Paulin

Andri

Conti

et al. 2021

IEEE Trans. VLSI Syst.

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Section: B Isa Extensions For Domain Specializationmentioning

confidence: 99%

Section: Comparison With Related Workmentioning

confidence: 99%

RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures

Paulin

Andri

Conti

et al. 2021

IEEE Trans. VLSI Syst.

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“…The architecture must implement the assembly instruction set with minimum hardware cost. The main advantages are flexibility and reduced time to market [6].…”

Section: Introductionmentioning

confidence: 99%

ASIPAMPIUM: An Efficient ASIP Generator for Low Power Applications

et al. 2023

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The adoption of customized ASIPs (Application Specific Instruction Set Processors) in embedded circuits is an important alternative for optimizing power consumption, silicon area, or processing performance according to the design requirements. The processor is implemented specifically for the target application, which allows the hardware customization in terms of instruction set architecture, data word length, memory size, and parallelism. This work describes an EDA tool for the semi-automatic development of ASIPs named ASIPAMPIUM. The strategy is to provide a set of integrated tools to interpret and generate a customized hardware for a given target application, including compilation, simulation, and hardware synthesis. From the C code description of the application, the tool returns a synthesizable hardware description of the processor. The proposed methodology is based on the adaptation of a new customizable microprocessor called PAMPIUM, which can be optimized in terms of silicon area, power consumption, or processing performance according to the target application. The ASIPAMPIUM tool provides a series of simulated data to the designer in order to identify optimization strategies in both software and hardware domains. We show the results for the implementation of an FFT algorithm using the proposed methodology, which achieved best results in terms of silicon area and energy consumption compared to other works described in the literature for both FPGA and silicon implementation. Moreover, measurement results of the implementation in silicon of a dedicated ASIP for interfacing with six sensors in real-time, including three I2C, an SPI, and an RS-232 interfaces, demonstrate the complete design flow, from the C code program to physical implementation and characterization. Aside from providing a short design time, the ASIPAMPIUM tool also affords a simple and intuitive design flow, allowing the designer to deal with different design trade-offs and objectives.

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“…Using different instruction combinations supported by our dedicated instruction set, different algorithms and functions can be realized with a relatively small number of hardware units. Using the design method of ASIPs, we can obtain higher flexibility than ASICs [13], leaving a design margin for the development of subsequent base station algorithms and extending the life cycle of the product. At the same time, compared with the CPU based on the general instruction set, the ASIP has lower power consumption and a smaller hardware area [14], which can reduce the construction cost of small cells.…”

Section: Introductionmentioning

confidence: 99%

An Uplink Channel Estimator Using a Dedicated Instruction Set for 5G Small Cells

Long

Liu

Sun

2022

Sensors

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As 5G small cells gradually become the main force of 5G indoor deployment, it is necessary to study channel estimators for 5G small base stations, but there has been limited research on high-performance channel estimators in recent years. This study implemented a low-delay, low-overhead, relatively universal channel estimation module by dedicated instruction set acceleration including reference signal estimation, Wiener, 1st order, and 2nd order interpolations in frequency and time domains. The instruction level acceleration is on our vector processor, yet is suitable for other commercial and academic vector processors. Through instruction acceleration, compared with the existing general vector processing instruction sets, the processor performance of the LS estimation module and Wiener filter interpolation in the frequency domain is improved by 50% and 37.5%, respectively. The BER VS SNR measure of time–frequency Wiener filter interpolation achieves 4 db compared with linear interpolation, meaning our instruction level acceleration can be an optimum solution.

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ASIP for 5G and Beyond: Opportunities and Vision

Cited by 7 publications

References 69 publications

RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures

RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures

ASIPAMPIUM: An Efficient ASIP Generator for Low Power Applications

An Uplink Channel Estimator Using a Dedicated Instruction Set for 5G Small Cells

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